From patchwork Thu Sep 24 17:42:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 11798043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD42459D for ; Thu, 24 Sep 2020 17:39:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFCEC23899 for ; Thu, 24 Sep 2020 17:39:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BFCEC23899 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F8636E3AC; Thu, 24 Sep 2020 17:39:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFF656E3AA for ; Thu, 24 Sep 2020 17:38:58 +0000 (UTC) IronPort-SDR: d2UrADSl6sS81jMKi6f8tjZT/+5IipYrYfO2izj00G6g/TZ3iDNOiddnTBoV3dWXiJIqm1v7ZT 6JZ+yv5Qy8eA== X-IronPort-AV: E=McAfee;i="6000,8403,9754"; a="158666805" X-IronPort-AV: E=Sophos;i="5.77,298,1596524400"; d="scan'208";a="158666805" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2020 10:38:58 -0700 IronPort-SDR: yoSNUjzYlZjVaqZ8Q0q8Pqp6mJYW7XgiO+NPJiIIP4c1LQyGsZAmrSAtkLo0T9ogadUytiI5EX Bh90bWcuCivA== X-IronPort-AV: E=Sophos;i="5.77,298,1596524400"; d="scan'208";a="512259622" Received: from agangwar-mobl2.gar.corp.intel.com (HELO josouza-MOBL2.amr.corp.intel.com) ([10.254.4.73]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2020 10:38:58 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Sep 2020 10:42:00 -0700 Message-Id: <20200924174201.44021-2-jose.souza@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200924174201.44021-1-jose.souza@intel.com> References: <20200924174201.44021-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Due to the debugfs flag, has_psr2 in CRTC state could have a different value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO and selective fetch) to be set to not a expected state. So here only taking in consideration the parameter and debugfs flag when computing PSR state, this way the CRTC state will also have the correct state. intel_psr_fastset_force() was already broken as intel_psr_compute_config() was already only enabling PSR when psr_global_enabled() and all other PSR requirements are met. So some changes was required in this function, now it iterates over all connectors, if it is a eDP connector and is active force a modeset in the CRTC driving this connector, what will cause the new PSR state to be set based on the debugfs flag. v2: - end connector iterator in error cases Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 73 +++++++++++++----------- 1 file changed, 41 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4e09ae61d4aa..02f74b0ddec1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915) } } -static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *crtc_state) +static bool psr2_global_enabled(struct drm_i915_private *dev_priv) { - /* Cannot enable DSC and PSR2 simultaneously */ - drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && - crtc_state->has_psr2); - switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_DISABLE: case I915_PSR_DEBUG_FORCE_PSR1: return false; default: - return crtc_state->has_psr2; + return true; } } @@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + if (!psr2_global_enabled(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); + return false; + } + /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC @@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (intel_dp != dev_priv->psr.dp) return; - if (!psr_global_enabled(dev_priv)) + if (!psr_global_enabled(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); return; + } + /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms have a instance of PSR registers per transcoder but @@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); - dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); + dev_priv->psr.psr2_enabled = crtc_state->has_psr2; dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; @@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); mutex_lock(&dev_priv->psr.lock); - - if (!psr_global_enabled(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); - goto unlock; - } - intel_psr_enable_locked(dev_priv, crtc_state, conn_state); - -unlock: mutex_unlock(&dev_priv->psr.lock); } @@ -1222,8 +1217,8 @@ void intel_psr_update(struct intel_dp *intel_dp, mutex_lock(&dev_priv->psr.lock); - enable = crtc_state->has_psr && psr_global_enabled(dev_priv); - psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); + enable = crtc_state->has_psr; + psr2_enable = crtc_state->has_psr2; if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ @@ -1320,11 +1315,12 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) { + struct drm_connector_list_iter conn_iter; struct drm_device *dev = &dev_priv->drm; struct drm_modeset_acquire_ctx ctx; struct drm_atomic_state *state; - struct intel_crtc *crtc; - int err; + struct drm_connector *conn; + int err = 0; state = drm_atomic_state_alloc(dev); if (!state) @@ -1334,25 +1330,38 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) state->acquire_ctx = &ctx; retry: - for_each_intel_crtc(dev, crtc) { - struct intel_crtc_state *crtc_state = - intel_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) { - err = PTR_ERR(crtc_state); - goto error; + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(conn, &conn_iter) { + struct drm_connector_state *conn_state; + struct drm_crtc_state *crtc_state; + + if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) + continue; + + conn_state = drm_atomic_get_connector_state(state, conn); + if (IS_ERR(conn_state)) { + err = PTR_ERR(conn_state); + break; } - if (crtc_state->hw.active && crtc_state->has_psr) { - /* Mark mode as changed to trigger a pipe->update() */ - crtc_state->uapi.mode_changed = true; + if (!conn_state->crtc) + continue; + + crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); + if (IS_ERR(crtc_state)) { + err = PTR_ERR(crtc_state); break; } + + /* Mark mode as changed to trigger a pipe->update() */ + crtc_state->mode_changed = true; } + drm_connector_list_iter_end(&conn_iter); - err = drm_atomic_commit(state); + if (err == 0) + err = drm_atomic_commit(state); -error: if (err == -EDEADLK) { drm_atomic_state_clear(state); err = drm_modeset_backoff(&ctx);