diff mbox series

[RFC,2/8] drm/edid: Parse MAX_FRL field from HFVSDB block

Message ID 20201006094719.24119-3-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series Add support for DP-HDMI2.1 PCON | expand

Commit Message

Nautiyal, Ankit K Oct. 6, 2020, 9:47 a.m. UTC 
From: Swati Sharma <swati2.sharma@intel.com>

This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.

Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 50 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h |  6 +++++
 2 files changed, 56 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 631125b46e04..d468ac91abb6 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4849,6 +4849,51 @@  static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
 		info->rgb_quant_range_selectable = true;
 }
 
+static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
+						const u8 *db)
+{
+     /* hf_vsdb 7:14 support needs to be added */
+
+    u8 max_frl_rate_per_lane;
+    struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
+
+    max_frl_rate_per_lane = (db[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
+
+    switch(max_frl_rate_per_lane) {
+    case 0:
+	    hdmi->max_lane = 0;
+	    hdmi->max_frl_rate_per_lane = 0;
+	    break;
+    case 1:
+	    hdmi->max_lane = 3;
+	    hdmi->max_frl_rate_per_lane = 3;
+	    break;
+    case 2:
+	    hdmi->max_lane = 3;
+	    hdmi->max_frl_rate_per_lane = 6;
+	    break;
+    case 3:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 6;
+	    break;
+    case 4:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 8;
+	    break;
+    case 5:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 10;
+	    break;
+    case 6:
+	    hdmi->max_lane = 4;
+	    hdmi->max_frl_rate_per_lane = 12;
+	    break;
+    default:
+	    DRM_DEBUG_KMS("max frl rate per lane 0x%x, reserved\n", max_frl_rate_per_lane);
+	    break;
+    }
+}
+
 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
 					       const u8 *db)
 {
@@ -4902,6 +4947,11 @@  static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
 		}
 	}
 
+	if (hf_vsdb[7]) {
+		    DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
+		    drm_parse_hdmi_21_additional_fields(connector, hf_vsdb);
+	}
+
 	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
 }
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 928136556174..aa6ae9c17ca4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -207,6 +207,12 @@  struct drm_hdmi_info {
 
 	/** @y420_dc_modes: bitmap of deep color support index */
 	u8 y420_dc_modes;
+
+	/** @max_frl_rate_per_lane: support fixed rate link */
+	u8 max_frl_rate_per_lane;
+
+	/** @max_lane: supported by sink */
+	u8 max_lane;
 };
 
 /**