| Message ID | 20201015220038.271740-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/rkl: Add new cdclk table | expand |
> -----Original Message----- > From: Matt Roper <matthew.d.roper@intel.com> > Sent: Thursday, October 15, 2020 3:01 PM > To: intel-gfx@lists.freedesktop.org > Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Srivatsa, Anusha > <anusha.srivatsa@intel.com> > Subject: [PATCH] drm/i915/rkl: Add new cdclk table > > A recent bspec update has provided a new cdclk table for RKL. All of the > cdclk values are the same as those we've been using on ICL, TGL, etc., but > we obtain them by doubling both the PLL ratio and CD2X divider numbers. > > Bspec: 49202 > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +++++++++++++++++++++- > 1 file changed, 31 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 7b46330fa69c..c449d28d0560 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1233,6 +1233,30 @@ static const struct intel_cdclk_vals > icl_cdclk_table[] = { > {} > }; > > +static const struct intel_cdclk_vals rkl_cdclk_table[] = { > + { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, > + { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, > + { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, > + { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, > + { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, > + { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, > + > + { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, > + { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, > + { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, > + { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, > + { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, > + { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, > + > + { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, > + { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, > + { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, > + { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, > + { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, > + { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, > + {} > +}; > + > static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) > { > const struct intel_cdclk_vals *table = dev_priv->cdclk.table; @@ - > 2823,7 +2847,13 @@ u32 intel_read_rawclk(struct drm_i915_private > *dev_priv) > */ > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) { > - if (INTEL_GEN(dev_priv) >= 12) { > + if (IS_ROCKETLAKE(dev_priv)) { > + dev_priv->display.set_cdclk = bxt_set_cdclk; > + dev_priv->display.bw_calc_min_cdclk = > skl_bw_calc_min_cdclk; > + dev_priv->display.modeset_calc_cdclk = > bxt_modeset_calc_cdclk; > + dev_priv->display.calc_voltage_level = > tgl_calc_voltage_level; > + dev_priv->cdclk.table = rkl_cdclk_table; > + } else if (INTEL_GEN(dev_priv) >= 12) { > dev_priv->display.set_cdclk = bxt_set_cdclk; > dev_priv->display.bw_calc_min_cdclk = > skl_bw_calc_min_cdclk; > dev_priv->display.modeset_calc_cdclk = > bxt_modeset_calc_cdclk; > -- > 2.24.1
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7b46330fa69c..c449d28d0560 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1233,6 +1233,30 @@ static const struct intel_cdclk_vals icl_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals rkl_cdclk_table[] = { + { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, + { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, + { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, + { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, + { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, + { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, + + { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, + { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, + { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, + { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, + { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, + { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, + + { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, + { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, + { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, + { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, + { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, + { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, + {} +}; + static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { const struct intel_cdclk_vals *table = dev_priv->cdclk.table; @@ -2823,7 +2847,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) */ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 12) { + if (IS_ROCKETLAKE(dev_priv)) { + dev_priv->display.set_cdclk = bxt_set_cdclk; + dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; + dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; + dev_priv->cdclk.table = rkl_cdclk_table; + } else if (INTEL_GEN(dev_priv) >= 12) { dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
A recent bspec update has provided a new cdclk table for RKL. All of the cdclk values are the same as those we've been using on ICL, TGL, etc., but we obtain them by doubling both the PLL ratio and CD2X divider numbers. Bspec: 49202 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-)