From patchwork Wed Oct 21 13:14:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11849053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8447C388F9 for ; Wed, 21 Oct 2020 13:14:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CEEE2224E for ; Wed, 21 Oct 2020 13:14:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4CEEE2224E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C6D6F6EB18; Wed, 21 Oct 2020 13:14:54 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D35336EB15 for ; Wed, 21 Oct 2020 13:14:52 +0000 (UTC) IronPort-SDR: /ipktWu+wPbwfCsevtK/doIKaoG1sO+FyRCtl5JYAXA5zFTqHmid06sB/y/Bobw4hX0dZ7iKMR 3D/ZwAF60tJg== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="228988525" X-IronPort-AV: E=Sophos;i="5.77,401,1596524400"; d="scan'208";a="228988525" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2020 06:14:52 -0700 IronPort-SDR: TwK86LJF32NGQgLYsZp7p3BUdMnmkeRmgJm9DpnFiGEpt2qQHLm7ge0Nq06N31uoTAWBHIfodl Wry8/E+L18IA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,401,1596524400"; d="scan'208";a="359497266" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 21 Oct 2020 06:14:50 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 21 Oct 2020 16:14:49 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Oct 2020 16:14:41 +0300 Message-Id: <20201021131443.25616-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201021131443.25616-1-ville.syrjala@linux.intel.com> References: <20201021131443.25616-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915: Fix potential overflows in ilk ips calculations X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä A bunch of the ips calculations require 64bit math. In particular 'corr' and 'corr2' look like they can overflow on 32bit systems. Switch to explicit u64 for those. Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_rps.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index e0db7541dbfa..1cf48c51a93e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1281,8 +1281,9 @@ static unsigned long __ips_gfx_val(struct intel_ips *ips) { struct intel_rps *rps = container_of(ips, typeof(*rps), ips); struct intel_uncore *uncore = rps_to_uncore(rps); - unsigned long t, corr, state1, corr2, state2; + unsigned int t, state1, state2; u32 pxvid, ext_v; + u64 corr, corr2; lockdep_assert_held(&mchdev_lock); @@ -1303,11 +1304,10 @@ static unsigned long __ips_gfx_val(struct intel_ips *ips) else /* < 50 */ corr = t * 301 + 1004; - corr = corr * 150142 * state1 / 10000 - 78642; - corr /= 100000; - corr2 = corr * ips->corr; + corr = div_u64(corr * 150142 * state1, 10000) - 78642; + corr2 = div_u64(corr, 100000) * ips->corr; - state2 = corr2 * state1 / 10000; + state2 = div_u64(corr2 * state1, 10000); state2 /= 100; /* convert to mW */ __gen5_ips_update(ips);