diff mbox series

[04/18] drm/i915/adl_s: Add Interrupt Support

Message ID 20201021133213.328994-5-aditya.swarup@intel.com
State New, archived
Headers show
Series Introduce Alderlake-S | expand

Commit Message

Aditya Swarup Oct. 21, 2020, 1:31 p.m. UTC
From: Anusha Srivatsa <anusha.srivatsa@intel.com>

ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting up hpd interrupts.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 19 insertions(+), 4 deletions(-)

Comments

Lucas De Marchi Oct. 21, 2020, 5:28 p.m. UTC | #1
On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>ADLS DDI and HPD masks for setting up hpd interrupts.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h |  3 +++
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index b753c77c9a77..9033221995ad 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)

you still need to assign hpd_pin to do the mapping between port and hpd
pin. Earlier this was done in the irq handler itself, but now is done in
intel_ddi_init(). See what I did for DG1:
https://patchwork.freedesktop.org/patch/396062/?series=82905&rev=1

Lucas De Marchi

> 	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
> 		return;
>
>-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>-	    HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>+	if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>+	    HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>+	    HAS_PCH_MCC(dev_priv))
> 		hpd->pch_hpd = hpd_icp;
> 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
> 		hpd->pch_hpd = hpd_spt;
>@@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> 	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> 	u32 pin_mask = 0, long_mask = 0;
>
>-	if (HAS_PCH_TGP(dev_priv)) {
>+	if (IS_ALDERLAKE_S(dev_priv)) {
>+		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>+		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>+	} else if (HAS_PCH_TGP(dev_priv)) {
> 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> 		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> 	} else if (HAS_PCH_JSP(dev_priv)) {
>@@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 			  TGP_DDI_HPD_ENABLE_MASK, 0);
> }
>
>+static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>+{
>+	icp_hpd_irq_setup(dev_priv,
>+			  ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>+}
>+
> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>@@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> 		if (I915_HAS_HOTPLUG(dev_priv))
> 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> 	} else {
>-		if (HAS_PCH_JSP(dev_priv))
>+		if (IS_ALDERLAKE_S(dev_priv))
>+			dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>+		else if (HAS_PCH_JSP(dev_priv))
> 			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
> 		else if (HAS_PCH_MCC(dev_priv))
> 			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 83ddea1cd174..f6b844ca7a9f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8343,6 +8343,7 @@ enum {
> 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
>+#define SDE_DDI_MASK_ADLS		 SDE_DDI_HOTPLUG_ICP(PORT_A)
>
> #define SDEISR  _MMIO(0xc4000)
> #define SDEIMR  _MMIO(0xc4004)
>@@ -8438,6 +8439,8 @@ enum {
> 					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
> 					 ICP_TC_HPD_ENABLE_MASK)
>
>+#define ADLS_DDI_HPD_ENABLE_MASK	 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>+
> #define _PCH_DPLL_A              0xc6014
> #define _PCH_DPLL_B              0xc6018
> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>-- 
>2.27.0
>
Aditya Swarup Oct. 22, 2020, 11:26 p.m. UTC | #2
On 10/21/20 10:28 AM, Lucas De Marchi wrote:
> On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>> ADLS DDI and HPD masks for setting up hpd interrupts.
>>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
>> drivers/gpu/drm/i915/i915_reg.h |  3 +++
>> 2 files changed, 19 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index b753c77c9a77..9033221995ad 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> 
> you still need to assign hpd_pin to do the mapping between port and hpd
> pin. Earlier this was done in the irq handler itself, but now is done in
> intel_ddi_init(). See what I did for DG1:
> https://patchwork.freedesktop.org/patch/396062/?series=82905&rev=1

I don't think that is required as for all Gen12+ platforms, tgl_hpd_pin is used for assignment
and the logic works for adl-s with PORT A mapping staying the same and for ports greater than
PORT D, HPD_PORT_TC1 is used as starting offset.

From intel_ddi_init()
else if (INTEL_GEN(dev_priv) >= 12)
                encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

Also, I have tested this code wrt hotplugs on the system and it works for all ports.

Regards,
Aditya Swarup
> 
> Lucas De Marchi
> 
>>     if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>>         return;
>>
>> -    if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>> -        HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>> +    if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>> +        HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>> +        HAS_PCH_MCC(dev_priv))
>>         hpd->pch_hpd = hpd_icp;
>>     else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
>>         hpd->pch_hpd = hpd_spt;
>> @@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>>     u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>>     u32 pin_mask = 0, long_mask = 0;
>>
>> -    if (HAS_PCH_TGP(dev_priv)) {
>> +    if (IS_ALDERLAKE_S(dev_priv)) {
>> +        ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>> +        tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> +    } else if (HAS_PCH_TGP(dev_priv)) {
>>         ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>>         tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>>     } else if (HAS_PCH_JSP(dev_priv)) {
>> @@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>               TGP_DDI_HPD_ENABLE_MASK, 0);
>> }
>>
>> +static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>> +{
>> +    icp_hpd_irq_setup(dev_priv,
>> +              ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>> +}
>> +
>> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>> {
>>     u32 hotplug;
>> @@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>         if (I915_HAS_HOTPLUG(dev_priv))
>>             dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>>     } else {
>> -        if (HAS_PCH_JSP(dev_priv))
>> +        if (IS_ALDERLAKE_S(dev_priv))
>> +            dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>> +        else if (HAS_PCH_JSP(dev_priv))
>>             dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>>         else if (HAS_PCH_MCC(dev_priv))
>>             dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 83ddea1cd174..f6b844ca7a9f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8343,6 +8343,7 @@ enum {
>>                      SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>>                      SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>>                      SDE_TC_HOTPLUG_ICP(PORT_TC1))
>> +#define SDE_DDI_MASK_ADLS         SDE_DDI_HOTPLUG_ICP(PORT_A)
>>
>> #define SDEISR  _MMIO(0xc4000)
>> #define SDEIMR  _MMIO(0xc4004)
>> @@ -8438,6 +8439,8 @@ enum {
>>                      ICP_TC_HPD_ENABLE(PORT_TC5) | \
>>                      ICP_TC_HPD_ENABLE_MASK)
>>
>> +#define ADLS_DDI_HPD_ENABLE_MASK     SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>> +
>> #define _PCH_DPLL_A              0xc6014
>> #define _PCH_DPLL_B              0xc6018
>> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>> -- 
>> 2.27.0
>>
Lucas De Marchi Oct. 23, 2020, 12:40 a.m. UTC | #3
On Thu, Oct 22, 2020 at 04:26:15PM -0700, Aditya Swarup wrote:
>On 10/21/20 10:28 AM, Lucas De Marchi wrote:
>> On Wed, Oct 21, 2020 at 06:31:59AM -0700, Aditya Swarup wrote:
>>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>>
>>> ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
>>> ADLS DDI and HPD masks for setting up hpd interrupts.
>>>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Cc: Imre Deak <imre.deak@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
>>> drivers/gpu/drm/i915/i915_reg.h |  3 +++
>>> 2 files changed, 19 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>> index b753c77c9a77..9033221995ad 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>>
>> you still need to assign hpd_pin to do the mapping between port and hpd
>> pin. Earlier this was done in the irq handler itself, but now is done in
>> intel_ddi_init(). See what I did for DG1:
>> https://patchwork.freedesktop.org/patch/396062/?series=82905&rev=1
>
>I don't think that is required as for all Gen12+ platforms, tgl_hpd_pin is used for assignment
>and the logic works for adl-s with PORT A mapping staying the same and for ports greater than
>PORT D, HPD_PORT_TC1 is used as starting offset.
>
>From intel_ddi_init()
>else if (INTEL_GEN(dev_priv) >= 12)
>                encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);

right... this is not like rkl/dg1 in which the hpd doesn't match the
port.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>
>Also, I have tested this code wrt hotplugs on the system and it works for all ports.
>
>Regards,
>Aditya Swarup
>>
>> Lucas De Marchi
>>
>>>     if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
>>>         return;
>>>
>>> -    if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
>>> -        HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
>>> +    if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
>>> +        HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
>>> +        HAS_PCH_MCC(dev_priv))
>>>         hpd->pch_hpd = hpd_icp;
>>>     else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
>>>         hpd->pch_hpd = hpd_spt;
>>> @@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>>>     u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>>>     u32 pin_mask = 0, long_mask = 0;
>>>
>>> -    if (HAS_PCH_TGP(dev_priv)) {
>>> +    if (IS_ALDERLAKE_S(dev_priv)) {
>>> +        ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
>>> +        tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>>> +    } else if (HAS_PCH_TGP(dev_priv)) {
>>>         ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>>>         tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>>>     } else if (HAS_PCH_JSP(dev_priv)) {
>>> @@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>>               TGP_DDI_HPD_ENABLE_MASK, 0);
>>> }
>>>
>>> +static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>> +{
>>> +    icp_hpd_irq_setup(dev_priv,
>>> +              ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
>>> +}
>>> +
>>> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>>> {
>>>     u32 hotplug;
>>> @@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>>         if (I915_HAS_HOTPLUG(dev_priv))
>>>             dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>>>     } else {
>>> -        if (HAS_PCH_JSP(dev_priv))
>>> +        if (IS_ALDERLAKE_S(dev_priv))
>>> +            dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
>>> +        else if (HAS_PCH_JSP(dev_priv))
>>>             dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
>>>         else if (HAS_PCH_MCC(dev_priv))
>>>             dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 83ddea1cd174..f6b844ca7a9f 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -8343,6 +8343,7 @@ enum {
>>>                      SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>>>                      SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>>>                      SDE_TC_HOTPLUG_ICP(PORT_TC1))
>>> +#define SDE_DDI_MASK_ADLS         SDE_DDI_HOTPLUG_ICP(PORT_A)
>>>
>>> #define SDEISR  _MMIO(0xc4000)
>>> #define SDEIMR  _MMIO(0xc4004)
>>> @@ -8438,6 +8439,8 @@ enum {
>>>                      ICP_TC_HPD_ENABLE(PORT_TC5) | \
>>>                      ICP_TC_HPD_ENABLE_MASK)
>>>
>>> +#define ADLS_DDI_HPD_ENABLE_MASK     SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
>>> +
>>> #define _PCH_DPLL_A              0xc6014
>>> #define _PCH_DPLL_B              0xc6018
>>> #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
>>> -- 
>>> 2.27.0
>>>
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b753c77c9a77..9033221995ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,8 +179,9 @@  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
 		return;
 
-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
-	    HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
+	    HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
+	    HAS_PCH_MCC(dev_priv))
 		hpd->pch_hpd = hpd_icp;
 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 		hpd->pch_hpd = hpd_spt;
@@ -1864,7 +1865,10 @@  static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
 	u32 pin_mask = 0, long_mask = 0;
 
-	if (HAS_PCH_TGP(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv)) {
+		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
+		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
+	} else if (HAS_PCH_TGP(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
 		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
 	} else if (HAS_PCH_JSP(dev_priv)) {
@@ -3252,6 +3256,12 @@  static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 			  TGP_DDI_HPD_ENABLE_MASK, 0);
 }
 
+static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+	icp_hpd_irq_setup(dev_priv,
+			  ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+}
+
 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -4162,7 +4172,9 @@  void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
 	} else {
-		if (HAS_PCH_JSP(dev_priv))
+		if (IS_ALDERLAKE_S(dev_priv))
+			dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
+		else if (HAS_PCH_JSP(dev_priv))
 			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
 		else if (HAS_PCH_MCC(dev_priv))
 			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 83ddea1cd174..f6b844ca7a9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8343,6 +8343,7 @@  enum {
 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_ADLS		 SDE_DDI_HOTPLUG_ICP(PORT_A)
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8438,6 +8439,8 @@  enum {
 					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
 
+#define ADLS_DDI_HPD_ENABLE_MASK	 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
+
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)