From patchwork Fri Oct 23 13:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11853509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3B1EC4363A for ; Fri, 23 Oct 2020 13:35:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 84F3F208E4 for ; Fri, 23 Oct 2020 13:35:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 84F3F208E4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D973B6F886; Fri, 23 Oct 2020 13:35:30 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B6A256F885 for ; Fri, 23 Oct 2020 13:35:27 +0000 (UTC) IronPort-SDR: ek/4CdxCgpEsxWwAjPb0ZizSk+lqbCVxzjVKimQG0lj2DchcsceqTNNP5uGmszJmh0XpNqnLRK EvDvAKeDqyAg== X-IronPort-AV: E=McAfee;i="6000,8403,9782"; a="146966730" X-IronPort-AV: E=Sophos;i="5.77,408,1596524400"; d="scan'208";a="146966730" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2020 06:35:27 -0700 IronPort-SDR: 6PPbtpY0eCHu4gWe24vFxKStQ6NIYZmFs9smAszxREQ3IQiJLmXF0OxrYCfjlK2h16GAhCkJ81 WHjcV5R9zh1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,408,1596524400"; d="scan'208";a="302764943" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 23 Oct 2020 06:35:25 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 23 Oct 2020 16:35:25 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Oct 2020 16:34:20 +0300 Message-Id: <20201023133420.12039-20-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201023133420.12039-1-ville.syrjala@linux.intel.com> References: <20201023133420.12039-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä ibx_irq_pre_postinstall() looks totally pointless. We can just init both SDEIMR and SDEIER at the same time before enabling the master intererupt. It's equally racy as the other order due to doing all of this from the postinstall stage with the interrupt handler already in place. That is, safe with MSI but racy with shared legacy interrupts. Fortunately we should have MSI on all ilk+. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++--------------------- 1 file changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b4eddf49a62a..25648ea990fc 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2898,24 +2898,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv) I915_WRITE(SERR_INT, 0xffffffff); } -/* - * SDEIER is also touched by the interrupt handler to work around missed PCH - * interrupts. Hence we can't update it after the interrupt handler is enabled - - * instead we unconditionally enable all PCH interrupt sources here, but then - * only unmask them as needed with SDEIMR. - * - * This function needs to be called before interrupts are enabled. - */ -static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv) -{ - if (HAS_PCH_NOP(dev_priv)) - return; - - drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0); - I915_WRITE(SDEIER, 0xffffffff); - POSTING_READ(SDEIER); -} - static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; @@ -3519,8 +3501,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) bxt_hpd_detection_setup(dev_priv); } +/* + * SDEIER is also touched by the interrupt handler to work around missed PCH + * interrupts. Hence we can't update it after the interrupt handler is enabled - + * instead we unconditionally enable all PCH interrupt sources here, but then + * only unmask them as needed with SDEIMR. + * + * Note that we currently do this after installing the interrupt handler, + * but before we enable the master interrupt. That should be sufficient + * to avoid races with the irq handler, assuming we have MSI. Shared legacy + * interrupts could still race. + */ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; u32 mask; if (HAS_PCH_NOP(dev_priv)) @@ -3533,8 +3527,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) else mask = SDE_GMBUS_CPT; - gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); - I915_WRITE(SDEIMR, ~mask); + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); } static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3567,14 +3560,12 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->irq_mask = ~display_mask; - ibx_irq_pre_postinstall(dev_priv); + ibx_irq_postinstall(dev_priv); gen5_gt_irq_postinstall(&dev_priv->gt); GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, display_mask | extra_mask); - - ibx_irq_postinstall(dev_priv); } void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) @@ -3699,15 +3690,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) { - if (HAS_PCH_SPLIT(dev_priv)) - ibx_irq_pre_postinstall(dev_priv); - - gen8_gt_irq_postinstall(&dev_priv->gt); - gen8_de_irq_postinstall(dev_priv); - if (HAS_PCH_SPLIT(dev_priv)) ibx_irq_postinstall(dev_priv); + gen8_gt_irq_postinstall(&dev_priv->gt); + gen8_de_irq_postinstall(dev_priv); + gen8_master_intr_enable(dev_priv->uncore.regs); }