From patchwork Tue Oct 27 20:39:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11861845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36613C388F9 for ; Tue, 27 Oct 2020 20:40:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD22720878 for ; Tue, 27 Oct 2020 20:40:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD22720878 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 465116EC46; Tue, 27 Oct 2020 20:40:17 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBDF36EC46 for ; Tue, 27 Oct 2020 20:40:13 +0000 (UTC) IronPort-SDR: n/LzyEbqsfthvTUuFDaGS66RJRouRVkU114WnMDdaKvOkkXSzlX6j/amYZirr3Q50iBpKgn6l9 /DrNXfDJ5OMQ== X-IronPort-AV: E=McAfee;i="6000,8403,9787"; a="155938039" X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="155938039" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 13:40:13 -0700 IronPort-SDR: tc2MMfe8mnNuu6RcHOHk/bdhlUdmC8Ia4231eAOXL18q++3i+QANokrn+ruT93g8BWBGXti/Nr 4bFINEn/QaYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,424,1596524400"; d="scan'208";a="361527772" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 27 Oct 2020 13:40:11 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 27 Oct 2020 22:40:10 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2020 22:39:52 +0200 Message-Id: <20201027203955.28032-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201027203955.28032-1-ville.syrjala@linux.intel.com> References: <20201027203955.28032-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/8] drm/i915: Move pipe ddb entries into the dbuf state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The dbuf state will be where we collect all the inter-pipe dbuf allocation stuff. Start by moving the actual per-pipe ddb entries there. v2: Rebase Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++------- .../drm/i915/display/intel_display_types.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 16 ++++++-------- drivers/gpu/drm/i915/intel_pm.h | 4 ++++ 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f41b6f8b5618..cb2f06fc1123 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15673,6 +15673,10 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state) static void skl_commit_modeset_enables(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + const struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; @@ -15687,7 +15691,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) /* ignore allocations for crtc's that have been turned off. */ if (!needs_modeset(new_crtc_state)) { - entries[pipe] = old_crtc_state->wm.skl.ddb; + entries[pipe] = old_dbuf_state->ddb[pipe]; update_pipes |= BIT(pipe); } else { modeset_pipes |= BIT(pipe); @@ -15711,11 +15715,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + if (skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe], entries, I915_MAX_PIPES, pipe)) continue; - entries[pipe] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_dbuf_state->ddb[pipe]; update_pipes &= ~BIT(pipe); intel_update_crtc(state, crtc); @@ -15726,8 +15730,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) * then we need to wait for a vblank to pass for the * new ddb allocation to take effect. */ - if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, - &old_crtc_state->wm.skl.ddb) && + if (!skl_ddb_entry_equal(&new_dbuf_state->ddb[pipe], + &old_dbuf_state->ddb[pipe]) && (update_pipes | modeset_pipes)) intel_wait_for_vblank(dev_priv, pipe); } @@ -15778,10 +15782,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, I915_MAX_PIPES, pipe)); + drm_WARN_ON(&dev_priv->drm, + skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe], + entries, I915_MAX_PIPES, pipe)); - entries[pipe] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_dbuf_state->ddb[pipe]; update_pipes &= ~BIT(pipe); intel_update_crtc(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f6f0626649e0..a4b5c06a1181 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -757,7 +757,6 @@ struct intel_crtc_wm_state { struct { /* gen9+ only needs 1-step wm programming */ struct skl_pipe_wm optimal; - struct skl_ddb_entry ddb; struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; } skl; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e4917454ec07..2ec48d9522e8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4154,16 +4154,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, * grab _all_ crtc locks, including the one we currently hold. */ if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && - !dev_priv->wm.distrust_bios_wm) { - /* - * alloc may be cleared by clear_intel_crtc_state, - * copy from old state to be sure - * - * FIXME get rid of this mess - */ - *alloc = to_intel_crtc_state(for_crtc->base.state)->wm.skl.ddb; + !dev_priv->wm.distrust_bios_wm) return 0; - } /* * Get allowed DBuf slices for correspondent pipe and platform. @@ -4790,7 +4782,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + struct intel_dbuf_state *dbuf_state = + intel_atomic_get_new_dbuf_state(state); + struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; u16 alloc_size, start = 0; u16 total[I915_MAX_PLANES] = {}; u16 uv_total[I915_MAX_PLANES] = {}; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 00910bc01407..724204bb8442 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -9,8 +9,10 @@ #include #include "display/intel_bw.h" +#include "display/intel_display.h" #include "display/intel_global_state.h" +#include "i915_drv.h" #include "i915_reg.h" struct drm_device; @@ -68,6 +70,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); struct intel_dbuf_state { struct intel_global_state base; + struct skl_ddb_entry ddb[I915_MAX_PIPES]; + u8 enabled_slices; u8 active_pipes; };