Message ID | 20201027234526.33043-5-jose.souza@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers | expand |
It works properly on a normal rgba plane. In order to apply this patch, the commit messaged need to be polished. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote: > Do the calculation of x and y offsets using > skl_calc_main_surface_offset(). > > RFC/WIP: This causes the value of the calculated x to be different > than > plane_state->color_plane[color_plane].x, not sure if that is > expected. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 96ee51484dd6..00c76ea82f92 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1188,7 +1188,8 @@ void intel_psr2_program_plane_sel_fetch(struct > intel_plane *plane, > struct drm_i915_private *dev_priv = to_i915(plane->base.dev); > enum pipe pipe = plane->pipe; > const struct drm_rect *clip; > - u32 val; > + u32 val, offset; > + int ret, x, y; > > if (!crtc_state->enable_psr2_sel_fetch) > return; > @@ -1205,9 +1206,14 @@ void intel_psr2_program_plane_sel_fetch(struct > intel_plane *plane, > val |= plane_state->uapi.dst.x1; > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane- > >id), val); > > - /* TODO: consider tiling and auxiliary surfaces */ > - val = (clip->y1 + plane_state->color_plane[color_plane].y) << > 16; > - val |= plane_state->color_plane[color_plane].x; > + /* TODO: consider auxiliary surfaces */ > + x = plane_state->uapi.src.x1 >> 16; > + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; > + ret = skl_calc_main_surface_offset(plane_state, &x, &y, > &offset); > + if (ret) > + drm_warn_once(&dev_priv->drm, > "skl_calc_main_surface_offset() returned %i\n", > + ret); > + val = y << 16 | x; > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane- > >id), > val); >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 96ee51484dd6..00c76ea82f92 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1188,7 +1188,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; const struct drm_rect *clip; - u32 val; + u32 val, offset; + int ret, x, y; if (!crtc_state->enable_psr2_sel_fetch) return; @@ -1205,9 +1206,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, val |= plane_state->uapi.dst.x1; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); - /* TODO: consider tiling and auxiliary surfaces */ - val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16; - val |= plane_state->color_plane[color_plane].x; + /* TODO: consider auxiliary surfaces */ + x = plane_state->uapi.src.x1 >> 16; + y = (plane_state->uapi.src.y1 >> 16) + clip->y1; + ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); + if (ret) + drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n", + ret); + val = y << 16 | x; intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), val);
Do the calculation of x and y offsets using skl_calc_main_surface_offset(). RFC/WIP: This causes the value of the calculated x to be different than plane_state->color_plane[color_plane].x, not sure if that is expected. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)