diff mbox series

drm/i915/jsl: Disable cursor clock gating in HDR mode

Message ID 20201028111731.137873-1-tejaskumarx.surendrakumar.upadhyay@intel.com
State New, archived
Headers show
Series drm/i915/jsl: Disable cursor clock gating in HDR mode | expand

Commit Message

Surendrakumar Upadhyay, TejaskumarX Oct. 28, 2020, 11:17 a.m. UTC
Display underrun in HDR mode when cursor is enabled.
RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
As per W/A 1604331009, Disable cursor clock gating in HDR mode.

Bspec : 33451

Cc: Souza Jose <jose.souza@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 32 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  5 +++
 2 files changed, 37 insertions(+)

Comments

Chris Wilson Oct. 28, 2020, 12:20 p.m. UTC | #1
Quoting Tejas Upadhyay (2020-10-28 11:17:31)
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> 
> Bspec : 33451
> 
> Cc: Souza Jose <jose.souza@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 32 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  5 +++
>  2 files changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f41b6f8b5618..73c4a43e6e31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -541,6 +541,19 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
>                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
>  }
>  
> +/* Wa_1604331009:jsl */
> +static void
> +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
> +                      bool enable)
> +{
> +       if (enable)
> +               intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
> +                              intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | CURSOR_GATING_DIS);
> +       else
> +               intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
> +                              intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~CURSOR_GATING_DIS);

intel_de_rmw(i915, CLKGATE_DIS_PSL(pipe),
	CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0);
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..73c4a43e6e31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -541,6 +541,19 @@  icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 }
 
+/* Wa_1604331009:jsl */
+static void
+jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
+		       bool enable)
+{
+	if (enable)
+		intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
+			       intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | CURSOR_GATING_DIS);
+	else
+		intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
+			       intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~CURSOR_GATING_DIS);
+}
+
 static bool
 needs_modeset(const struct intel_crtc_state *state)
 {
@@ -6637,6 +6650,16 @@  static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 	return false;
 }
 
+static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	/* Wa_1604331009:jsl */
+	if (crtc_state->active_planes & icl_hdr_plane_mask() &&
+	    IS_GEN(dev_priv, 11))
+		return true;
+	return false;
+}
+
 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 			    const struct intel_crtc_state *new_crtc_state)
 {
@@ -6678,6 +6701,10 @@  static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (needs_scalerclk_wa(old_crtc_state) &&
 	    !needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, pipe, false);
+
+	if (needs_cursorclk_wa(old_crtc_state) &&
+	    !needs_cursorclk_wa(new_crtc_state))
+		jsl_wa_cursorclkgating(dev_priv, pipe, false);
 }
 
 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
@@ -6743,6 +6770,11 @@  static void intel_pre_plane_update(struct intel_atomic_state *state,
 	    needs_scalerclk_wa(new_crtc_state))
 		icl_wa_scalerclkgating(dev_priv, pipe, true);
 
+	/* Wa_1604331009:jsl */
+	if (!needs_cursorclk_wa(old_crtc_state) &&
+	    needs_cursorclk_wa(new_crtc_state))
+		jsl_wa_cursorclkgating(dev_priv, pipe, true);
+
 	/*
 	 * Vblank time updates from the shadow to live plane control register
 	 * are blocked if the memory self-refresh mode is active at that
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b021f77cb1f..0434cab4bebb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4194,6 +4194,11 @@  enum {
 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
 #define   CGPSF_CLKGATE_DIS		(1 << 3)
 
+/*
+ * GEN11 clock gating regs
+ */
+#define   CURSOR_GATING_DIS		BIT(28)
+
 /*
  * Display engine regs
  */