diff mbox series

[v3,18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+

Message ID 20201028213323.5423-19-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Futher cleanup around hpd pins and port identfiers | expand

Commit Message

Ville Syrjala Oct. 28, 2020, 9:33 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason not to use GEN3_IRQ_INIT() on icp+.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2337416e581c..95268fca2fbc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3739,14 +3739,10 @@  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask = SDE_GMBUS_ICP;
 
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)