From patchwork Wed Oct 28 21:33:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11863145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F903C4363A for ; Wed, 28 Oct 2020 21:33:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ABDF724844 for ; Wed, 28 Oct 2020 21:33:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ABDF724844 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 061B76E5AE; Wed, 28 Oct 2020 21:33:53 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46F0C6E58B for ; Wed, 28 Oct 2020 21:33:51 +0000 (UTC) IronPort-SDR: 0agPRFeYvGA0bc4kcNUXWNHfjSbemXhDFm6ZFseEcO2gjz7k+G98M74XodAVNKSBVY9yvdzoz1 OekOJCJH9EkA== X-IronPort-AV: E=McAfee;i="6000,8403,9788"; a="165751478" X-IronPort-AV: E=Sophos;i="5.77,428,1596524400"; d="scan'208";a="165751478" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2020 14:33:49 -0700 IronPort-SDR: Lq9PXylzno9XmGd9u4pQdeu3EINQ1ajNHDWWM0Bp4q9lSVvecF/4L+9iZEgAlzCboRMQ9+BC5A n2/jDMPwdDrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,428,1596524400"; d="scan'208";a="394956903" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 28 Oct 2020 14:33:47 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 28 Oct 2020 23:33:46 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 28 Oct 2020 23:33:12 +0200 Message-Id: <20201028213323.5423-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201028213323.5423-1-ville.syrjala@linux.intel.com> References: <20201028213323.5423-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Unify the BDW/BXT hotplug bits. BDW only has port A, but that matches BXT port A so we can shar the same macro for both. v2: Remember the gvt Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/gvt/display.c | 14 +++++++------- drivers/gpu/drm/i915/i915_irq.c | 18 +++++++++--------- drivers/gpu/drm/i915/i915_reg.h | 10 +++++----- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index c124734e114c..5b5c71a0b4af 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) if (IS_BROXTON(dev_priv)) { vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= - ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) | - BXT_DE_PORT_HP_DDI(HPD_PORT_B) | - BXT_DE_PORT_HP_DDI(HPD_PORT_C)); + ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | + GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | + GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= - BXT_DE_PORT_HP_DDI(HPD_PORT_A); + GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); } if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= - BXT_DE_PORT_HP_DDI(HPD_PORT_B); + GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); } if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= - BXT_DE_PORT_HP_DDI(HPD_PORT_C); + GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); } return; @@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { if (IS_BROADWELL(dev_priv)) vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= - GEN8_PORT_DP_A_HOTPLUG; + GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); else vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 252464d90575..216d6247b30a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = { }; static const u32 hpd_bdw[HPD_NUM_PINS] = { - [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, + [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), }; static const u32 hpd_ibx[HPD_NUM_PINS] = { @@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { }; static const u32 hpd_bxt[HPD_NUM_PINS] = { - [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A), - [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B), - [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C), + [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), + [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), + [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), }; static const u32 hpd_gen11[HPD_NUM_PINS] = { @@ -2379,7 +2379,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } } else if (IS_BROADWELL(dev_priv)) { - tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; + tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK; if (tmp_mask) { ilk_hpd_irq_handler(dev_priv, tmp_mask); found = true; @@ -3420,13 +3420,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, * For BXT invert bit has to be set based on AOB design * for HPD detection logic, update it based on VBT fields. */ - if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) && + if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) hotplug |= BXT_DDIA_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) && + if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) hotplug |= BXT_DDIB_HPD_INVERT; - if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) && + if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) && intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) hotplug |= BXT_DDIC_HPD_INVERT; @@ -3595,7 +3595,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (IS_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; else if (IS_BROADWELL(dev_priv)) - de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; + de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; if (INTEL_GEN(dev_priv) >= 12) { enum transcoder trans; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 37038afd404f..950d2bd7d7a8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7827,11 +7827,11 @@ enum { #define GEN9_AUX_CHANNEL_B (1 << 25) #define DSI1_TE (1 << 24) #define DSI0_TE (1 << 23) -#define BXT_DE_PORT_HP_DDI(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) -#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \ - BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \ - BXT_DE_PORT_HP_DDI(HPD_PORT_C)) -#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) +#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) +#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ + GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ + GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) +#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) #define BXT_DE_PORT_GMBUS (1 << 1) #define GEN8_AUX_CHANNEL_A (1 << 0) #define TGL_DE_PORT_AUX_USBC6 (1 << 13)