From patchwork Fri Oct 30 16:50:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11870281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACFD3C00A89 for ; Fri, 30 Oct 2020 16:50:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4893620725 for ; Fri, 30 Oct 2020 16:50:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4893620725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FAE26E9D6; Fri, 30 Oct 2020 16:50:56 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FD516E9D6 for ; Fri, 30 Oct 2020 16:50:55 +0000 (UTC) IronPort-SDR: j8YXSNjFHmadxomqCOb6ZmbjuIqvKqwXRiwLeK3Xl602nG85oj3XQPA+2RogzK1JnWeE4FxEw7 OaBHhBnir1oQ== X-IronPort-AV: E=McAfee;i="6000,8403,9790"; a="253342079" X-IronPort-AV: E=Sophos;i="5.77,434,1596524400"; d="scan'208";a="253342079" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2020 09:50:54 -0700 IronPort-SDR: 3gkTfJORMaaaug8l1E17wU/9C0UGzVE+T4D2P3LBaa2bFUAG1Py9f04pUwE8xzsFAAS8tK6dKL eyd3VD2UiC3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,434,1596524400"; d="scan'208";a="335475567" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 30 Oct 2020 09:50:52 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 30 Oct 2020 18:50:51 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Oct 2020 18:50:37 +0200 Message-Id: <20201030165045.5000-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201030165045.5000-1-ville.syrjala@linux.intel.com> References: <20201030165045.5000-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/10] drm/i915: Shrink ilk-bdw wm storage by using u16 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The maximum watermark value we can ever have on ilk-bdw is 11 bits. Thus we can safely store all of these values in u16. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h | 8 +- drivers/gpu/drm/i915/intel_pm.c | 74 +++++++++---------- 2 files changed, 40 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f6f0626649e0..4c25e2e4f4ee 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -666,10 +666,10 @@ struct intel_crtc_scaler_state { struct intel_wm_level { bool enable; - u32 pri_val; - u32 spr_val; - u32 cur_val; - u32 fbc_val; + u16 pri_val; + u16 spr_val; + u16 cur_val; + u16 fbc_val; }; struct intel_pipe_wm { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 75d2322cd456..a82fb812b8c7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1225,9 +1225,9 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state, return dirty; } -static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, +static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, - u32 pri_val); + u16 pri_val); static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) @@ -2506,7 +2506,7 @@ static unsigned int ilk_wm_method1(unsigned int pixel_rate, ret = intel_wm_method1(pixel_rate, cpp, latency); ret = DIV_ROUND_UP(ret, 64) + 2; - return ret; + return min_t(unsigned int, ret, U16_MAX); } /* latency must be in 0.1us units. */ @@ -2522,10 +2522,11 @@ static unsigned int ilk_wm_method2(unsigned int pixel_rate, width, cpp, latency); ret = DIV_ROUND_UP(ret, 64) + 2; - return ret; + return min_t(unsigned int, ret, U16_MAX); } -static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp) +static u16 ilk_wm_fbc(u16 pri_val, unsigned int horiz_pixels, + unsigned int cpp) { /* * Neither of these should be possible since this function shouldn't be @@ -2552,15 +2553,15 @@ struct ilk_wm_maximums { * For both WM_PIPE and WM_LP. * mem_value must be in 0.1us units. */ -static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state, +static u16 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, - u32 mem_value, bool is_lp) + unsigned int mem_value, bool is_lp) { - u32 method1, method2; + u16 method1, method2; int cpp; if (mem_value == 0) - return U32_MAX; + return U16_MAX; if (!intel_wm_plane_visible(crtc_state, plane_state)) return 0; @@ -2584,15 +2585,15 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state, * For both WM_PIPE and WM_LP. * mem_value must be in 0.1us units. */ -static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state, +static u16 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, - u32 mem_value) + unsigned int mem_value) { - u32 method1, method2; + u16 method1, method2; int cpp; if (mem_value == 0) - return U32_MAX; + return U16_MAX; if (!intel_wm_plane_visible(crtc_state, plane_state)) return 0; @@ -2611,14 +2612,14 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state, * For both WM_PIPE and WM_LP. * mem_value must be in 0.1us units. */ -static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state, +static u16 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, - u32 mem_value) + unsigned int mem_value) { int cpp; if (mem_value == 0) - return U32_MAX; + return U16_MAX; if (!intel_wm_plane_visible(crtc_state, plane_state)) return 0; @@ -2632,9 +2633,9 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state, } /* Only for WM_LP. */ -static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, +static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, - u32 pri_val) + u16 pri_val) { int cpp; @@ -2647,8 +2648,7 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, cpp); } -static unsigned int -ilk_display_fifo_size(const struct drm_i915_private *dev_priv) +static u16 ilk_display_fifo_size(const struct drm_i915_private *dev_priv) { if (INTEL_GEN(dev_priv) >= 8) return 3072; @@ -2658,9 +2658,8 @@ ilk_display_fifo_size(const struct drm_i915_private *dev_priv) return 512; } -static unsigned int -ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, - int level, bool is_sprite) +static u16 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, + int level, bool is_sprite) { if (INTEL_GEN(dev_priv) >= 8) /* BDW primary/sprite plane watermarks */ @@ -2676,8 +2675,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, return level == 0 ? 63 : 255; } -static unsigned int -ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) +static u16 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) { if (INTEL_GEN(dev_priv) >= 7) return level == 0 ? 63 : 255; @@ -2685,7 +2683,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) return level == 0 ? 31 : 63; } -static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) +static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) { if (INTEL_GEN(dev_priv) >= 8) return 31; @@ -2694,13 +2692,13 @@ static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) } /* Calculate the maximum primary/sprite plane watermark */ -static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, - int level, - const struct intel_wm_config *config, - enum intel_ddb_partitioning ddb_partitioning, - bool is_sprite) +static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv, + int level, + const struct intel_wm_config *config, + enum intel_ddb_partitioning ddb_partitioning, + bool is_sprite) { - unsigned int fifo_size = ilk_display_fifo_size(dev_priv); + u16 fifo_size = ilk_display_fifo_size(dev_priv); /* if sprites aren't enabled, sprites get nothing */ if (is_sprite && !config->sprites_enabled) @@ -2735,9 +2733,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, } /* Calculate the maximum cursor plane watermark */ -static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, - int level, - const struct intel_wm_config *config) +static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, + int level, + const struct intel_wm_config *config) { /* HSW LP1+ watermarks w/ multiple pipes */ if (level > 0 && config->num_pipes_active > 1) @@ -2801,9 +2799,9 @@ static bool ilk_validate_wm_level(int level, DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", level, result->cur_val, max->cur); - result->pri_val = min_t(u32, result->pri_val, max->pri); - result->spr_val = min_t(u32, result->spr_val, max->spr); - result->cur_val = min_t(u32, result->cur_val, max->cur); + result->pri_val = min(result->pri_val, max->pri); + result->spr_val = min(result->spr_val, max->spr); + result->cur_val = min(result->cur_val, max->cur); result->enable = true; }