@@ -3791,8 +3791,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
-#define MCH_SSKPD_WM0_MASK 0x3f
-#define MCH_SSKPD_WM0_VAL 0xc
/* Clocking configuration register */
#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
@@ -6982,17 +6982,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
}
}
-static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
-{
- u32 tmp;
-
- tmp = I915_READ(MCH_SSKPD);
- if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
- drm_dbg_kms(&dev_priv->drm,
- "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
- tmp);
-}
-
static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
{
u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -7050,8 +7039,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
g4x_disable_trickle_feed(dev_priv);
cpt_init_clock_gating(dev_priv);
-
- gen6_check_mch_setup(dev_priv);
}
static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7420,8 +7407,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
if (!HAS_PCH_NOP(dev_priv))
cpt_init_clock_gating(dev_priv);
-
- gen6_check_mch_setup(dev_priv);
}
static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)