From patchwork Sun Nov 15 21:07:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11906855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BC7FC61DD8 for ; Sun, 15 Nov 2020 21:08:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E48D22447 for ; Sun, 15 Nov 2020 21:08:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2E48D22447 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2701A6E9C7; Sun, 15 Nov 2020 21:08:18 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 413D06E9C6 for ; Sun, 15 Nov 2020 21:08:17 +0000 (UTC) IronPort-SDR: pS8nGQ5yyAYFdi+zxtjk7YQM6/jNaP/KoZ/YC8r9lul1QV1bzjW2sWg3EoMJ/hp/g8e9SxYB/y 71mFLzjMLuOg== X-IronPort-AV: E=McAfee;i="6000,8403,9806"; a="158455839" X-IronPort-AV: E=Sophos;i="5.77,481,1596524400"; d="scan'208";a="158455839" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2020 13:08:16 -0800 IronPort-SDR: 9KXu9LEaZLoT7AJsDa5Onj5UDOzaFQHx6OVk7jM4t2WtW3ibQ0qW8M4uJJtmQa37Ob5of9TrQ2 k5Xo7MrTx5dQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,481,1596524400"; d="scan'208";a="430009557" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by fmsmga001.fm.intel.com with ESMTP; 15 Nov 2020 13:08:15 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Sun, 15 Nov 2020 13:07:55 -0800 Message-Id: <20201115210815.5272-7-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201115210815.5272-1-sean.z.huang@intel.com> References: <20201115210815.5272-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [PATCH 07/27] drm/i915/pxp: Add PXP-related registers into allowlist X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add several PXP-related reg into allowlist to allow ring3 driver to read the those register values. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++ drivers/gpu/drm/i915/intel_uncore.c | 57 +++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index faf6b06145fa..5c51c9df8b28 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12419,4 +12419,12 @@ enum skl_power_gate { #define TGL_ROOT_DEVICE_SKU_ULX 0x2 #define TGL_ROOT_DEVICE_SKU_ULT 0x4 +/* Registers for passlist check */ +#define PXP_REG_01_LOWERBOUND _MMIO(0x32260) +#define PXP_REG_01_UPPERBOUND _MMIO(0x32268) +#define PXP_REG_02_LOWERBOUND _MMIO(0x32670) +#define PXP_REG_02_UPPERBOUND _MMIO(0x32678) +#define PXP_REG_03_LOWERBOUND _MMIO(0x32860) +#define PXP_REG_03_UPPERBOUND _MMIO(0x32c7c) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index c9ef0025c60e..670856e095c4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1990,16 +1990,41 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore) } static const struct reg_allowlist { - i915_reg_t offset_ldw; + i915_reg_t offset_ldw_lowerbound; + i915_reg_t offset_ldw_upperbound; i915_reg_t offset_udw; u16 gen_mask; u8 size; -} reg_read_allowlist[] = { { - .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), +} reg_read_allowlist[] = { + { + .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE), + .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE), .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), .gen_mask = INTEL_GEN_MASK(4, 12), .size = 8 -} }; + }, + { + .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND, + .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND, + .offset_udw = {0}, + .gen_mask = INTEL_GEN_MASK(4, 12), + .size = 4 + }, + { + .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND, + .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND, + .offset_udw = {0}, + .gen_mask = INTEL_GEN_MASK(4, 12), + .size = 4 + }, + { + .offset_ldw_lowerbound = PXP_REG_03_LOWERBOUND, + .offset_ldw_upperbound = PXP_REG_03_UPPERBOUND, + .offset_udw = {0}, + .gen_mask = INTEL_GEN_MASK(4, 12), + .size = 4 + } +}; int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file) @@ -2012,18 +2037,22 @@ int i915_reg_read_ioctl(struct drm_device *dev, unsigned int flags; int remain; int ret = 0; + i915_reg_t offset_ldw; entry = reg_read_allowlist; remain = ARRAY_SIZE(reg_read_allowlist); while (remain) { - u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); + u32 entry_offset_lb = i915_mmio_reg_offset(entry->offset_ldw_lowerbound); + u32 entry_offset_ub = i915_mmio_reg_offset(entry->offset_ldw_upperbound); GEM_BUG_ON(!is_power_of_2(entry->size)); GEM_BUG_ON(entry->size > 8); - GEM_BUG_ON(entry_offset & (entry->size - 1)); + GEM_BUG_ON(entry_offset_lb & (entry->size - 1)); + GEM_BUG_ON(entry_offset_ub & (entry->size - 1)); if (INTEL_INFO(i915)->gen_mask & entry->gen_mask && - entry_offset == (reg->offset & -entry->size)) + entry_offset_lb <= (reg->offset & -entry->size) && + (reg->offset & -entry->size) <= entry_offset_ub) break; entry++; remain--; @@ -2033,23 +2062,21 @@ int i915_reg_read_ioctl(struct drm_device *dev, return -EINVAL; flags = reg->offset & (entry->size - 1); + offset_ldw = _MMIO(reg->offset - flags); with_intel_runtime_pm(&i915->runtime_pm, wakeref) { if (entry->size == 8 && flags == I915_REG_READ_8B_WA) reg->val = intel_uncore_read64_2x32(uncore, - entry->offset_ldw, + offset_ldw, entry->offset_udw); else if (entry->size == 8 && flags == 0) - reg->val = intel_uncore_read64(uncore, - entry->offset_ldw); + reg->val = intel_uncore_read64(uncore, offset_ldw); else if (entry->size == 4 && flags == 0) - reg->val = intel_uncore_read(uncore, entry->offset_ldw); + reg->val = intel_uncore_read(uncore, offset_ldw); else if (entry->size == 2 && flags == 0) - reg->val = intel_uncore_read16(uncore, - entry->offset_ldw); + reg->val = intel_uncore_read16(uncore, offset_ldw); else if (entry->size == 1 && flags == 0) - reg->val = intel_uncore_read8(uncore, - entry->offset_ldw); + reg->val = intel_uncore_read8(uncore, offset_ldw); else ret = -EINVAL; }