From patchwork Tue Nov 17 18:50:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11913265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE146C63697 for ; Tue, 17 Nov 2020 18:50:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C18724180 for ; Tue, 17 Nov 2020 18:50:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C18724180 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A9B9C89FED; Tue, 17 Nov 2020 18:50:53 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id EB3DF89FA9 for ; Tue, 17 Nov 2020 18:50:52 +0000 (UTC) IronPort-SDR: QjxH3Gjubp173Aq15wCgayfDEWJvuLYmJ0O21jQUwalZ53SXVGlnT9ZjB5vWP8C2bLW5RNdNvu pi3VcTJGXIDQ== X-IronPort-AV: E=McAfee;i="6000,8403,9808"; a="168412288" X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="168412288" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2020 10:50:49 -0800 IronPort-SDR: pAUDdCfe/j9FwynHVVrDZyq/Io9ZS18EPPG0tuz/grnSm5Pi9HWK4uvbEzlA97QIwZ4VsrCU8U nkL1+dXzYK5A== X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="340996876" Received: from ankithac-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.101.215]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2020 10:50:49 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Tue, 17 Nov 2020 10:50:19 -0800 Message-Id: <20201117185029.22078-12-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201117185029.22078-1-aditya.swarup@intel.com> References: <20201117185029.22078-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E. Combo PHY A still uses the old ddc pin mapping. From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI B->ddc_pin=2 should translate to PORT_D->0x9 DDI C->ddc_pin=3 should translate to PORT_E->0xa DDI D->ddc_pin=4 should translate to PORT_F->0xb DDI E->ddc_pin=5 should translate to PORT_G->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI B and DDI C info. Bspec:20124 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4cc949b228f2..716a15f87632 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = { [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, }; +static const u8 adls_ddc_pin_map[] = { + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { const u8 *ddc_pin_map; int n_entries; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { + if (IS_ALDERLAKE_S(dev_priv)) { + ddc_pin_map = adls_ddc_pin_map; + n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { return vbt_pin; } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { ddc_pin_map = icp_ddc_pin_map; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index f90838bc74fb..8fdf0623d663 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3145,6 +3145,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return intel_port_to_phy(dev_priv, port) + 1; } +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + enum phy phy = intel_port_to_phy(dev_priv, port); + + WARN_ON(port == PORT_B || port == PORT_C); + + /* + * Pin mapping for ADL-S requires TC pins for all combo phy outputs + * except first combo output. + */ + if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B) + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; + + return GMBUS_PIN_1_BXT + phy; +} + static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { @@ -3182,7 +3198,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + if (IS_ALDERLAKE_S(dev_priv)) + ddc_pin = adls_port_to_ddc_pin(dev_priv, port); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 49b4b5fca941..32d1b4f05760 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -325,6 +325,10 @@ enum vbt_gmbus_ddi { ICL_DDC_BUS_PORT_4, TGL_DDC_BUS_PORT_5, TGL_DDC_BUS_PORT_6, + ADLS_DDC_BUS_PORT_TC1 = 0x2, + ADLS_DDC_BUS_PORT_TC2, + ADLS_DDC_BUS_PORT_TC3, + ADLS_DDC_BUS_PORT_TC4 }; #define DP_AUX_A 0x40