diff mbox series

[16/21] drm/i915/adl_s: MCHBAR memory info registers are moved

Message ID 20201117185029.22078-17-aditya.swarup@intel.com (mailing list archive)
State New, archived
Headers show
Series Introduce Alderlake-S | expand

Commit Message

Aditya Swarup Nov. 17, 2020, 6:50 p.m. UTC
From: Caz Yokoyama <caz.yokoyama@intel.com>

The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
 drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

Comments

Lucas De Marchi Nov. 20, 2020, 8:18 p.m. UTC | #1
On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
>From: Caz Yokoyama <caz.yokoyama@intel.com>
>
>The crwebview indicates on ADL-S that some of our MCHBAR
>registers have moved from their traditional 0x50XX offsets to
>new locations. The meaning and bit layout of the registers
>remain same.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
> drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
> 2 files changed, 20 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 4c8d0d84af6a..6abba59592f7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10863,6 +10863,8 @@ enum skl_power_gate {
> #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
> #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
>
>+#define  ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
>+
> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> #define  SKL_DRAM_S_SHIFT			16
>@@ -10890,6 +10892,9 @@ enum skl_power_gate {
> #define  CNL_DRAM_RANK_3			(0x2 << 9)
> #define  CNL_DRAM_RANK_4			(0x3 << 9)
>
>+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>+
> /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>  * since on HSW we can't write to it using I915_WRITE. */
> #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4754296a250e..e7427e5f4130 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> 	u32 val;
> 	int ret;
>
>-	val = intel_uncore_read(&i915->uncore,
>+	if (IS_ALDERLAKE_S(i915))
>+		val = intel_uncore_read(&i915->uncore,
>+				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
>+	else
>+		val = intel_uncore_read(&i915->uncore,
> 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
> 	if (ret == 0)
> 		dram_info->num_channels++;
>
>-	val = intel_uncore_read(&i915->uncore,
>+	if (IS_ALDERLAKE_S(i915))
>+		val = intel_uncore_read(&i915->uncore,
>+				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
>+	else
>+		val = intel_uncore_read(&i915->uncore,
> 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);

probably better to:

u32 ch0, ch1;

and then keep the reads together in a single if/else chain.
Or use i915_reg_t ch0_reg, ch1_reg

Lucas De Marchi

> 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
> 	if (ret == 0)
>@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
> {
> 	u32 val;
>
>-	val = intel_uncore_read(&i915->uncore,
>+	if (IS_ALDERLAKE_S(i915))
>+		val = intel_uncore_read(&i915->uncore,
>+				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
>+	else
>+		val = intel_uncore_read(&i915->uncore,
> 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
>
> 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {
>-- 
>2.27.0
>
Caz Yokoyama Nov. 20, 2020, 8:39 p.m. UTC | #2
On Fri, 2020-11-20 at 12:18 -0800, Lucas De Marchi wrote:
> On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
> > From: Caz Yokoyama <caz.yokoyama@intel.com>
> > 
> > The crwebview indicates on ADL-S that some of our MCHBAR
> > registers have moved from their traditional 0x50XX offsets to
> > new locations. The meaning and bit layout of the registers
> > remain same.
> > 
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
> > drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
> > 2 files changed, 20 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4c8d0d84af6a..6abba59592f7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10863,6 +10863,8 @@ enum skl_power_gate {
> > #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
> > #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
> > 
> > +#define  ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
> > +
> > #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x500C)
> > #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x5010)
> > #define  SKL_DRAM_S_SHIFT			16
> > @@ -10890,6 +10892,9 @@ enum skl_power_gate {
> > #define  CNL_DRAM_RANK_3			(0x2 << 9)
> > #define  CNL_DRAM_RANK_4			(0x3 << 9)
> > 
> > +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x6054)
> > +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x6058)
> > +
> > /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using
> > this register,
> >  * since on HSW we can't write to it using I915_WRITE. */
> > #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB +
> > 0x5F0C)
> > diff --git a/drivers/gpu/drm/i915/intel_dram.c
> > b/drivers/gpu/drm/i915/intel_dram.c
> > index 4754296a250e..e7427e5f4130 100644
> > --- a/drivers/gpu/drm/i915/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > @@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct
> > drm_i915_private *i915)
> > 	u32 val;
> > 	int ret;
> > 
> > -	val = intel_uncore_read(&i915->uncore,
> > +	if (IS_ALDERLAKE_S(i915))
> > +		val = intel_uncore_read(&i915->uncore,
> > +				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
> > +	else
> > +		val = intel_uncore_read(&i915->uncore,
> > 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> > 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
> > 	if (ret == 0)
> > 		dram_info->num_channels++;
> > 
> > -	val = intel_uncore_read(&i915->uncore,
> > +	if (IS_ALDERLAKE_S(i915))
> > +		val = intel_uncore_read(&i915->uncore,
> > +				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
> > +	else
> > +		val = intel_uncore_read(&i915->uncore,
> > 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> 
> probably better to:
> 
> u32 ch0, ch1;
> 
> and then keep the reads together in a single if/else chain.
> Or use i915_reg_t ch0_reg, ch1_reg
Agree/Better idea. When I worked for, I only concerned how to minimize
my patch and not think about whether the code is simple and readable. 
-caz

> 
> Lucas De Marchi
> 
> > 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
> > 	if (ret == 0)
> > @@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private
> > *i915)
> > {
> > 	u32 val;
> > 
> > -	val = intel_uncore_read(&i915->uncore,
> > +	if (IS_ALDERLAKE_S(i915))
> > +		val = intel_uncore_read(&i915->uncore,
> > +				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
> > +	else
> > +		val = intel_uncore_read(&i915->uncore,
> > 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMA
> > IN);
> > 
> > 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {
> > -- 
> > 2.27.0
> >
Lucas De Marchi Nov. 25, 2020, 12:11 a.m. UTC | #3
On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
>From: Caz Yokoyama <caz.yokoyama@intel.com>
>
>The crwebview indicates on ADL-S that some of our MCHBAR
>registers have moved from their traditional 0x50XX offsets to
>new locations. The meaning and bit layout of the registers
>remain same.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Yokoyama, Caz <caz.yokoyama@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
> drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++---
> 2 files changed, 20 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 4c8d0d84af6a..6abba59592f7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10863,6 +10863,8 @@ enum skl_power_gate {
> #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
> #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
>
>+#define  ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)

should be single space after define

Lucas De Marchi

>+
> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> #define  SKL_DRAM_S_SHIFT			16
>@@ -10890,6 +10892,9 @@ enum skl_power_gate {
> #define  CNL_DRAM_RANK_3			(0x2 << 9)
> #define  CNL_DRAM_RANK_4			(0x3 << 9)
>
>+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>+
> /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>  * since on HSW we can't write to it using I915_WRITE. */
> #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4754296a250e..e7427e5f4130 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> 	u32 val;
> 	int ret;
>
>-	val = intel_uncore_read(&i915->uncore,
>+	if (IS_ALDERLAKE_S(i915))
>+		val = intel_uncore_read(&i915->uncore,
>+				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
>+	else
>+		val = intel_uncore_read(&i915->uncore,
> 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
> 	if (ret == 0)
> 		dram_info->num_channels++;
>
>-	val = intel_uncore_read(&i915->uncore,
>+	if (IS_ALDERLAKE_S(i915))
>+		val = intel_uncore_read(&i915->uncore,
>+				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
>+	else
>+		val = intel_uncore_read(&i915->uncore,
> 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
> 	if (ret == 0)
>@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
> {
> 	u32 val;
>
>-	val = intel_uncore_read(&i915->uncore,
>+	if (IS_ALDERLAKE_S(i915))
>+		val = intel_uncore_read(&i915->uncore,
>+				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
>+	else
>+		val = intel_uncore_read(&i915->uncore,
> 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
>
> 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {
>-- 
>2.27.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c8d0d84af6a..6abba59592f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10863,6 +10863,8 @@  enum skl_power_gate {
 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
 
+#define  ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
+
 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
 #define  SKL_DRAM_S_SHIFT			16
@@ -10890,6 +10892,9 @@  enum skl_power_gate {
 #define  CNL_DRAM_RANK_3			(0x2 << 9)
 #define  CNL_DRAM_RANK_4			(0x3 << 9)
 
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..e7427e5f4130 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -184,13 +184,21 @@  skl_dram_get_channels_info(struct drm_i915_private *i915)
 	u32 val;
 	int ret;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
 	if (ret == 0)
 		dram_info->num_channels++;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
 	if (ret == 0)
@@ -231,7 +239,11 @@  skl_get_dram_type(struct drm_i915_private *i915)
 {
 	u32 val;
 
-	val = intel_uncore_read(&i915->uncore,
+	if (IS_ALDERLAKE_S(i915))
+		val = intel_uncore_read(&i915->uncore,
+				ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+	else
+		val = intel_uncore_read(&i915->uncore,
 				SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 
 	switch (val & SKL_DRAM_DDR_TYPE_MASK) {