From patchwork Tue Nov 17 18:50:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11913283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04085C63697 for ; Tue, 17 Nov 2020 18:51:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A18CE238E6 for ; Tue, 17 Nov 2020 18:51:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A18CE238E6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C61E6E045; Tue, 17 Nov 2020 18:51:09 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F4C189FCC for ; Tue, 17 Nov 2020 18:50:53 +0000 (UTC) IronPort-SDR: Fgg3D/9GXAOLnV+o2ulhCoXTYTCvvXGDy/i32a4ujKWPYjJDk+RlQNFPqBh/Eb3DIzQZnE1CBf gLKpDrzyWrsg== X-IronPort-AV: E=McAfee;i="6000,8403,9808"; a="168412297" X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="168412297" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2020 10:50:52 -0800 IronPort-SDR: D9e/tdCpc43imDApjsWHq3GX90+zOdd2Ed9CbpHbX07MqZEv17s14gs6jR/4v8kEK2Yb4ktZQp RPyiuRE9LVrA== X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="340996903" Received: from ankithac-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.101.215]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2020 10:50:52 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Tue, 17 Nov 2020 10:50:24 -0800 Message-Id: <20201117185029.22078-17-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201117185029.22078-1-aditya.swarup@intel.com> References: <20201117185029.22078-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi , Yokoyama@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama The crwebview indicates on ADL-S that some of our MCHBAR registers have moved from their traditional 0x50XX offsets to new locations. The meaning and bit layout of the registers remain same. Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Signed-off-by: Yokoyama, Caz Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_dram.c | 18 +++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4c8d0d84af6a..6abba59592f7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10863,6 +10863,8 @@ enum skl_power_gate { #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048) + #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) #define SKL_DRAM_S_SHIFT 16 @@ -10890,6 +10892,9 @@ enum skl_power_gate { #define CNL_DRAM_RANK_3 (0x2 << 9) #define CNL_DRAM_RANK_4 (0x3 << 9) +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054) +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058) + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 4754296a250e..e7427e5f4130 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915) u32 val; int ret; - val = intel_uncore_read(&i915->uncore, + if (IS_ALDERLAKE_S(i915)) + val = intel_uncore_read(&i915->uncore, + ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR); + else + val = intel_uncore_read(&i915->uncore, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); ret = skl_dram_get_channel_info(i915, &ch0, 0, val); if (ret == 0) dram_info->num_channels++; - val = intel_uncore_read(&i915->uncore, + if (IS_ALDERLAKE_S(i915)) + val = intel_uncore_read(&i915->uncore, + ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR); + else + val = intel_uncore_read(&i915->uncore, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); ret = skl_dram_get_channel_info(i915, &ch1, 1, val); if (ret == 0) @@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915) { u32 val; - val = intel_uncore_read(&i915->uncore, + if (IS_ALDERLAKE_S(i915)) + val = intel_uncore_read(&i915->uncore, + ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR); + else + val = intel_uncore_read(&i915->uncore, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); switch (val & SKL_DRAM_DDR_TYPE_MASK) {