From patchwork Wed Nov 18 03:30:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 11913799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DA12C2D0E4 for ; Wed, 18 Nov 2020 03:25:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0A8124695 for ; Wed, 18 Nov 2020 03:25:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0A8124695 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8C8F6E284; Wed, 18 Nov 2020 03:25:39 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C8116E284 for ; Wed, 18 Nov 2020 03:25:39 +0000 (UTC) IronPort-SDR: 55ijV0D5vatZYBU3qCvztKt3OYBaMz8osSAQHTGvZTOne/shSnBNh4+JYayYGhyP358ouPM79+ fALOgT/Z+u/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9808"; a="158832718" X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="158832718" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2020 19:25:38 -0800 IronPort-SDR: Vln8eCQCnJoHXPN+I8XjlWCxbyjvgoRgU6t92x4zDu4U0PupRfLqTOrWPUpIZXqqM58uUM3eRh 4z14h4m4mHhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="368113298" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.9]) by FMSMGA003.fm.intel.com with ESMTP; 17 Nov 2020 19:25:36 -0800 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Wed, 18 Nov 2020 11:30:25 +0800 Message-Id: <20201118033025.25454-1-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201116135913.20782-1-shawn.c.lee@intel.com> References: <20201116135913.20782-1-shawn.c.lee@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/lspcon: enter standby mode to enhance power saving X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After system boot up, LSPCON will be configured as PCON mode. But it never go into power saving state. Source driver can do the following. Then LSPCON can enter standby mode automatically to save more power. 1. At PCON mode, source driver write 0x2 to DPCD 600h. 2. At LS mode, try to disable DP_DUAL_MODE_TMDS_OEN. v2: fix typo Cc: Ville Syrjälä Cc: Jani Nikula Cc: Uma Shankar Cc: Cooper Chiou Cc: Khaled Almahallawy Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++- drivers/gpu/drm/i915/display/intel_lspcon.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_lspcon.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ec8359f03aaf..7dd16d6bd5ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6536,6 +6536,7 @@ intel_dp_detect(struct drm_connector *connector, struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); struct intel_encoder *encoder = &dig_port->base; enum drm_connector_status status; @@ -6632,9 +6633,13 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_check_service_irq(intel_dp); out: - if (status != connector_status_connected && !intel_dp->is_mst) + if (status != connector_status_connected && !intel_dp->is_mst) { intel_dp_unset_edid(intel_dp); + if (lspcon && lspcon->active) + lspcon_standby(dp_to_dig_port(intel_dp)); + } + /* * Make sure the refs for power wells enabled during detect are * dropped to avoid a new detect cycle triggered by HPD polling. diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index e37d45e531df..d9bc052d3bde 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -550,6 +550,14 @@ static bool lspcon_init(struct intel_digital_port *dig_port) return true; } +void lspcon_standby(struct intel_digital_port *dig_port) +{ + struct intel_dp *dp = &dig_port->dp; + + if (drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3) <= 0) + DRM_DEBUG_KMS("LSPCON failed to write power state to D3\n"); +} + void lspcon_resume(struct intel_digital_port *dig_port) { struct intel_lspcon *lspcon = &dig_port->lspcon; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index b03dcb7076d8..658a2e5b22db 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -16,6 +16,7 @@ struct intel_encoder; struct intel_lspcon; void lspcon_resume(struct intel_digital_port *dig_port); +void lspcon_standby(struct intel_digital_port *dig_port); void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); void lspcon_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state,