@@ -647,6 +647,8 @@ static int init_status_page(struct intel_engine_cs *engine)
void *vaddr;
int ret;
+ INIT_LIST_HEAD(&engine->status_page.timelines);
+
/*
* Though the HWS register does support 36bit addresses, historically
* we have had hangs and corruption reported due to wild writes if
@@ -68,6 +68,7 @@ typedef u8 intel_engine_mask_t;
#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
struct intel_hw_status_page {
+ struct list_head timelines;
struct i915_vma *vma;
u32 *addr;
};
@@ -4063,6 +4063,14 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
GEM_BUG_ON(READ_ONCE(*execlists->csb_write) != reset_value);
}
+static void sanitize_timelines(struct intel_engine_cs *engine)
+{
+ struct intel_timeline *tl;
+
+ list_for_each_entry(tl, &engine->status_page.timelines, engine_link)
+ intel_timeline_reset_seqno(tl);
+}
+
static void execlists_sanitize(struct intel_engine_cs *engine)
{
GEM_BUG_ON(execlists_active(&engine->execlists));
@@ -4086,7 +4094,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
* that may be lost on resume/initialisation, and so we need to
* reset the value in the HWSP.
*/
- intel_timeline_reset_seqno(engine->kernel_context->timeline);
+ sanitize_timelines(engine);
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
@@ -48,9 +48,16 @@ static inline struct intel_timeline *
intel_timeline_create_from_engine(struct intel_engine_cs *engine,
unsigned int offset)
{
- return __intel_timeline_create(engine->gt,
- engine->status_page.vma,
- offset);
+ struct intel_timeline *tl;
+
+ tl = __intel_timeline_create(engine->gt,
+ engine->status_page.vma,
+ offset);
+ if (IS_ERR(tl))
+ return tl;
+
+ list_add_tail(&tl->engine_link, &engine->status_page.timelines);
+ return tl;
}
static inline struct intel_timeline *
@@ -84,6 +84,8 @@ struct intel_timeline {
struct list_head link;
struct intel_gt *gt;
+ struct list_head engine_link;
+
struct kref kref;
struct rcu_head rcu;
};
We assume that the contents of the HWSP are lost across suspend, and so upon resume we must restore critical values such as the timeline seqno. Keep track of every timeline allocated that uses the HWSP as its storage and so we can then reset all seqno values by walking that list. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 10 +++++++++- drivers/gpu/drm/i915/gt/intel_timeline.h | 13 ++++++++++--- drivers/gpu/drm/i915/gt/intel_timeline_types.h | 2 ++ 5 files changed, 24 insertions(+), 4 deletions(-)