From patchwork Sat Dec 5 01:08:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 11952695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0123AC4361B for ; Sat, 5 Dec 2020 01:09:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C00C122D70 for ; Sat, 5 Dec 2020 01:09:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C00C122D70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9AE606E2D8; Sat, 5 Dec 2020 01:09:14 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 051AA6E2C7 for ; Sat, 5 Dec 2020 01:09:12 +0000 (UTC) IronPort-SDR: USn9M6kUXVprClUQPpUy1RuoZOUbdW+7qorwDE0TuFh8wyGHYxe4M0qqjvwW2c9B5beiUK5Mji Ovgj0ongvLYw== X-IronPort-AV: E=McAfee;i="6000,8403,9825"; a="173571031" X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="173571031" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:12 -0800 IronPort-SDR: PqbP0DKzYV8Ns2463+PcwLwGnpAP2ffrBpT9Il4OjV+R62ogUIrmo2D+wulE2EfYgxgaQYaeqx x+PsNGIR5ckg== X-IronPort-AV: E=Sophos;i="5.78,394,1599548400"; d="scan'208";a="369062997" Received: from msdesadl-mobl1.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.251.12.22]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2020 17:09:12 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Dec 2020 17:08:39 -0800 Message-Id: <20201205010844.361880-18-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com> References: <20201205010844.361880-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama The crwebview indicates on ADL-S that some of our MCHBAR registers have moved from their traditional 0x50XX offsets to new locations. The meaning and bit layout of the registers remain same. v2: Simplify logic to a single if else chain and fix indents.(Lucas) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Signed-off-by: Caz Yokoyama Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_dram.c | 23 +++++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce4ef7fa4000..55e186293fbb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10865,6 +10865,8 @@ enum skl_power_gate { #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048) + #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) #define SKL_DRAM_S_SHIFT 16 @@ -10892,6 +10894,9 @@ enum skl_power_gate { #define CNL_DRAM_RANK_3 (0x2 << 9) #define CNL_DRAM_RANK_4 (0x3 << 9) +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054) +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058) + /* * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using intel_uncore_write. diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 4754296a250e..fc9942139ccc 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915) { struct dram_info *dram_info = &i915->dram_info; struct dram_channel_info ch0 = {}, ch1 = {}; + i915_reg_t ch0_reg, ch1_reg; u32 val; int ret; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); + if (IS_ALDERLAKE_S(i915)) { + ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR; + ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR; + } else { + ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR; + ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR; + } + + val = intel_uncore_read(&i915->uncore, ch0_reg); ret = skl_dram_get_channel_info(i915, &ch0, 0, val); if (ret == 0) dram_info->num_channels++; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); + val = intel_uncore_read(&i915->uncore, ch1_reg); ret = skl_dram_get_channel_info(i915, &ch1, 1, val); if (ret == 0) dram_info->num_channels++; @@ -231,8 +238,12 @@ skl_get_dram_type(struct drm_i915_private *i915) { u32 val; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); + if (IS_ALDERLAKE_S(i915)) + val = intel_uncore_read(&i915->uncore, + ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR); + else + val = intel_uncore_read(&i915->uncore, + SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); switch (val & SKL_DRAM_DDR_TYPE_MASK) { case SKL_DRAM_DDR_TYPE_DDR3: