From patchwork Fri Dec 11 09:04:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Sean Z" X-Patchwork-Id: 11967701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B953BC1B0D9 for ; Fri, 11 Dec 2020 09:05:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D16C23E1B for ; Fri, 11 Dec 2020 09:05:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D16C23E1B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5350D6ECEF; Fri, 11 Dec 2020 09:05:39 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4BF286ECCC for ; Fri, 11 Dec 2020 09:05:33 +0000 (UTC) IronPort-SDR: OqjaoygByPPRrft3TFOx7NWL0Rb+MxIU3ZRe2SYBLD5jBRI/FRx+4bsiBOV/JT+Acdi820lKK6 klc2HkJYEmFA== X-IronPort-AV: E=McAfee;i="6000,8403,9831"; a="162159106" X-IronPort-AV: E=Sophos;i="5.78,410,1599548400"; d="scan'208";a="162159106" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2020 01:05:31 -0800 IronPort-SDR: 355HnrZYRHYn6x8r4BX6vUl3rD5FP5zDG7JWiWcn7zwifcnqZPBInS7U/XkOkHZOSIh/gILY3M gk+7Q4VQtHJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,410,1599548400"; d="scan'208";a="553804530" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by orsmga005.jf.intel.com with ESMTP; 11 Dec 2020 01:05:30 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Fri, 11 Dec 2020 01:04:42 -0800 Message-Id: <20201211090457.32674-9-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201211090457.32674-1-sean.z.huang@intel.com> References: <20201211090457.32674-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v8 08/23] drm/i915/pxp: Enable PXP power management X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During the power event S3+ sleep/resume, hardware will lose all the encryption keys for every hardware session, even though the software session state was marked as alive after resume. So to handle such case, PXP should terminate all the hardware sessions and cleanup all the software states after the power cycle. Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++ drivers/gpu/drm/i915/i915_drv.c | 4 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++++++++++ 6 files changed, 106 insertions(+) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index abe52189986a..d419dfa4923d 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \ pxp/intel_pxp_arb.o \ pxp/intel_pxp_cmd.o \ pxp/intel_pxp_context.o \ + pxp/intel_pxp_pm.o \ pxp/intel_pxp_tee.o # Post-mortem debug and GPU hang state capture diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 274aa0dd7050..09a64d0feafe 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -20,6 +20,7 @@ #include "intel_rc6.h" #include "intel_rps.h" #include "intel_wakeref.h" +#include "pxp/intel_pxp_pm.h" static void user_forcewake(struct intel_gt *gt, bool suspend) { @@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt) intel_uc_resume(>->uc); + intel_pxp_pm_resume(>->pxp); + user_forcewake(gt, false); out_fw: @@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt) user_forcewake(gt, true); wait_for_suspend(gt); + intel_pxp_pm_prepare_suspend(>->pxp); intel_uc_suspend(>->uc); } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9299a456adb0..af06c85e6ba7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -68,6 +68,8 @@ #include "gt/intel_gt_pm.h" #include "gt/intel_rc6.h" +#include "pxp/intel_pxp_pm.h" + #include "i915_debugfs.h" #include "i915_drv.h" #include "i915_ioc32.h" @@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_power_domains_resume(dev_priv); + intel_pxp_pm_resume_early(&dev_priv->gt.pxp); + enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h index 3ba891f9ac26..8d3308ac3120 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h @@ -20,6 +20,7 @@ struct pxp_context { int id; bool global_state_attacked; + bool global_state_in_suspend; bool flag_display_hm_surface_keys; }; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c new file mode 100644 index 000000000000..0da2ecbf3b4d --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2020 Intel Corporation. + */ + +#include "intel_pxp_context.h" +#include "intel_pxp_arb.h" +#include "intel_pxp_pm.h" + +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ + if (pxp->ctx.id == 0) + return; + + mutex_lock(&pxp->ctx.mutex); + + /* Disable PXP-IOCTLs */ + pxp->ctx.global_state_in_suspend = true; + + mutex_unlock(&pxp->ctx.mutex); +} + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ + if (pxp->ctx.id == 0) + return; + + mutex_lock(&pxp->ctx.mutex); + + if (pxp->ctx.global_state_in_suspend) { + /* reset the attacked flag even there was a pending */ + pxp->ctx.global_state_attacked = false; + + pxp->ctx.flag_display_hm_surface_keys = false; + } + + mutex_unlock(&pxp->ctx.mutex); +} + +int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + int ret = 0; + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp); + + if (pxp->ctx.id == 0) + return 0; + + mutex_lock(&pxp->ctx.mutex); + + /* Re-enable PXP-IOCTLs */ + if (pxp->ctx.global_state_in_suspend) { + ret = intel_pxp_arb_terminate_session(pxp); + if (ret) { + drm_err(>->i915->drm, "Failed to terminate the arb session\n"); + goto end; + } + + pxp->ctx.global_state_in_suspend = false; + } + +end: + mutex_unlock(&pxp->ctx.mutex); + + return ret; +} diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h new file mode 100644 index 000000000000..135bfb59aaf7 --- /dev/null +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2020, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_PXP_PM_H__ +#define __INTEL_PXP_PM_H__ + +#include "i915_drv.h" + +#ifdef CONFIG_DRM_I915_PXP +void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp); + +void intel_pxp_pm_resume_early(struct intel_pxp *pxp); +int intel_pxp_pm_resume(struct intel_pxp *pxp); +#else +static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp) +{ +} + +static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp) +{ +} + +static inline int intel_pxp_pm_resume(struct intel_pxp *pxp) +{ + return 0; +} +#endif + +#endif /* __INTEL_PXP_PM_H__ */