From patchwork Thu Jan 7 18:20:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12004641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54234C433DB for ; Thu, 7 Jan 2021 18:20:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D9B39207C8 for ; Thu, 7 Jan 2021 18:20:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D9B39207C8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 48E6D6E4C7; Thu, 7 Jan 2021 18:20:36 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2C656E4C7 for ; Thu, 7 Jan 2021 18:20:34 +0000 (UTC) IronPort-SDR: GGsTDakz9R6ciVh5o6OJI67pyQgxtdqnqJg1z5B4wFyyJ5J/Lr6pbS5R/C6rAoAMFtq5jgDmFr xxp5TpOPxa/w== X-IronPort-AV: E=McAfee;i="6000,8403,9857"; a="164542025" X-IronPort-AV: E=Sophos;i="5.79,329,1602572400"; d="scan'208";a="164542025" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2021 10:20:34 -0800 IronPort-SDR: pSghWP+rl3Nf3vlNvcH0r1D9gZoS7BJ8mrnMVxizjRtH+WFXVP036vw5lGsTzUAgnRDl8FVWBU JPDPkMI09qRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,329,1602572400"; d="scan'208";a="463126546" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 07 Jan 2021 10:20:32 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 07 Jan 2021 20:20:31 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Jan 2021 20:20:26 +0200 Message-Id: <20210107182026.24848-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107182026.24848-1-ville.syrjala@linux.intel.com> References: <20210107182026.24848-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm: Refactor intel_dp_compute_link_config_*() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pull the common parts of intel_dp_compute_link_config_wide() and intel_dp_compute_link_config_fast() into a shared helper to avoid duplicated code. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 74 ++++++++++++++----------- 1 file changed, 43 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 57c2140c1316..d682cf57e455 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2259,34 +2259,47 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, } } +static bool +intel_dp_link_config_valid(const struct intel_crtc_state *crtc_state, + int bpp, int link_clock, int lane_count) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int output_bpp = intel_dp_output_bpp(crtc_state->output_format, bpp); + int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, + output_bpp); + int link_avail = intel_dp_max_data_rate(link_clock, lane_count); + + return mode_rate <= link_avail; +} + /* Optimize link config in order: max bpp, min clock, min lanes */ static int intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, + struct intel_crtc_state *crtc_state, const struct link_config_limits *limits) { - struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int bpp, clock, lane_count; - int mode_rate, link_clock, link_avail; + int bpp; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { - int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); + int clock; - mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, - output_bpp); + for (clock = limits->min_clock; + clock <= limits->max_clock; + clock++) { + int lane_count; - for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - link_clock = intel_dp->common_rates[clock]; - link_avail = intel_dp_max_data_rate(link_clock, - lane_count); + int link_clock = intel_dp->common_rates[clock]; - if (mode_rate <= link_avail) { - pipe_config->lane_count = lane_count; - pipe_config->pipe_bpp = bpp; - pipe_config->port_clock = link_clock; + if (intel_dp_link_config_valid(crtc_state, bpp, + link_clock, + lane_count)) { + crtc_state->pipe_bpp = bpp; + crtc_state->port_clock = link_clock; + crtc_state->lane_count = lane_count; return 0; } @@ -2300,31 +2313,30 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, /* Optimize link config in order: max bpp, min lanes, min clock */ static int intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, + struct intel_crtc_state *crtc_state, const struct link_config_limits *limits) { - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int bpp, clock, lane_count; - int mode_rate, link_clock, link_avail; + int bpp; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { - int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); - - mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, - output_bpp); + int lane_count; for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { - link_clock = intel_dp->common_rates[clock]; - link_avail = intel_dp_max_data_rate(link_clock, - lane_count); + int clock; - if (mode_rate <= link_avail) { - pipe_config->lane_count = lane_count; - pipe_config->pipe_bpp = bpp; - pipe_config->port_clock = link_clock; + for (clock = limits->min_clock; + clock <= limits->max_clock; + clock++) { + int link_clock = intel_dp->common_rates[clock]; + + if (intel_dp_link_config_valid(crtc_state, bpp, + link_clock, + lane_count)) { + crtc_state->pipe_bpp = bpp; + crtc_state->port_clock = link_clock; + crtc_state->lane_count = lane_count; return 0; }