[v7,1/3] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

Commit Message

Imre Deak Jan. 14, 2021, 8:13 p.m. UTC

From: Radhakrishna Sripada <[e-mail]>

Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.

V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)

Cc: Ville Syrjala <[e-mail]>
Cc: Dhinakaran Pandiyan <[e-mail]>
Cc: Kalyan Kondapally <[e-mail]>
Cc: Rafael Antognolli <[e-mail]>
Cc: Nanley Chery <[e-mail]>
Signed-off-by: Radhakrishna Sripada <[e-mail]>
Signed-off-by: Imre Deak <[e-mail]>
Acked-by: Daniel Vetter <[e-mail]>
Acked-by: Jani Nikula <[e-mail]>
---
 include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Kahola, Mika Jan. 15, 2021, 9:41 a.m. UTC | #1

> -----Original Message-----
> From: Intel-gfx <[e-mail]> On Behalf Of Imre
> Deak
> Sent: Thursday, January 14, 2021 10:13 PM
> To: [e-mail]
> Cc: Chery, Nanley G <[e-mail]>; Rafael Antognolli
> <[e-mail]>; Daniel Vetter <[e-mail]>;
> Nikula, Jani <[e-mail]>; Pandiyan, Dhinakaran
> <[e-mail]>; Kondapally, Kalyan
> <[e-mail]>
> Subject: [Intel-gfx] [PATCH v7 1/3] drm/framebuffer: Format modifier for
> Intel Gen 12 render compression with Clear Color
> 
> From: Radhakrishna Sripada <[e-mail]>
> 
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface was
> compressed by render engine.
> 
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
> 
> Cc: Ville Syrjala <[e-mail]>
> Cc: Dhinakaran Pandiyan <[e-mail]>
> Cc: Kalyan Kondapally <[e-mail]>
> Cc: Rafael Antognolli <[e-mail]>
> Cc: Nanley Chery <[e-mail]>
> Signed-off-by: Radhakrishna Sripada <[e-mail]>
> Signed-off-by: Imre Deak <[e-mail]>
> Acked-by: Daniel Vetter <[e-mail]>
> Acked-by: Jani Nikula <[e-mail]>
Looks ok to me.

Reviewed-by: Mika Kahola <[e-mail]>

> ---
>  include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h index 5f42a14481bd..f76de49c768f
> 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -527,6 +527,25 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
> 
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is
> +linear
> + * and at index 1. The clear color is stored at index 2, and the pitch
> +should
> + * be ignored. The clear color structure is 256 bits. The first 128
> +bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> +represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and
> +generates
> + * the converted clear color of size 64 bits. The first 32 bits store
> +the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> +Converted
> + * Clear Color value when applicable. The Converted Clear Color values
> +are
> + * consumed by the DE. The last 64 bits are used to store Color Discard
> +Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache
> +line
> + * corresponds to an area of 4x1 tiles in the main surface. The main
> +surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL,
> +8)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> --
> 2.25.1
> 
> _______________________________________________
> Intel-gfx mailing list
> [e-mail]
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Chery, Nanley G Jan. 15, 2021, 6:42 p.m. UTC | #2

> -----Original Message-----
> From: Imre Deak <[e-mail]>
> Sent: Thursday, January 14, 2021 12:13 PM
> To: [e-mail]
> Cc: Sripada, Radhakrishna <[e-mail]>; Ville Syrjala
> <[e-mail]>; Pandiyan, Dhinakaran
> <[e-mail]>; Kondapally, Kalyan
> <[e-mail]>; Rafael Antognolli
> <[e-mail]>; Chery, Nanley G
> <[e-mail]>; Daniel Vetter <[e-mail]>; Nikula,
> Jani <[e-mail]>
> Subject: [PATCH v7 1/3] drm/framebuffer: Format modifier for Intel Gen 12
> render compression with Clear Color
> 
> From: Radhakrishna Sripada <[e-mail]>
> 
> Gen12 display can decompress surfaces compressed by render engine with
> Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
> 
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
> 
> Cc: Ville Syrjala <[e-mail]>
> Cc: Dhinakaran Pandiyan <[e-mail]>
> Cc: Kalyan Kondapally <[e-mail]>
> Cc: Rafael Antognolli <[e-mail]>
> Cc: Nanley Chery <[e-mail]>
> Signed-off-by: Radhakrishna Sripada <[e-mail]>
> Signed-off-by: Imre Deak <[e-mail]>
> Acked-by: Daniel Vetter <[e-mail]>
> Acked-by: Jani Nikula <[e-mail]>
> ---
>  include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 

Acked-by: Nanley Chery <[e-mail]>

> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> index 5f42a14481bd..f76de49c768f 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -527,6 +527,25 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
> 
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and
> generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard
> Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> --
> 2.25.1

Patch

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5f42a14481bd..f76de49c768f 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -527,6 +527,25 @@  extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *