| Message ID | 20210117093015.29143-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: Clear CACHE_MODE prior to clearing residuals | expand |
> -----Original Message----- > From: Chris Wilson <chris@chris-wilson.co.uk> > Sent: Sunday, January 17, 2021 1:30 AM > To: intel-gfx@lists.freedesktop.org > Cc: Chris Wilson <chris@chris-wilson.co.uk>; Mika Kuoppala > <mika.kuoppala@linux.intel.com>; Abodunrin, Akeem G > <akeem.g.abodunrin@intel.com> > Subject: [PATCH] drm/i915/gt: Clear CACHE_MODE prior to clearing residuals > > Since we do a bare context switch with no restore, the clear residual kernel > runs on dirty state, and we must be careful to avoid executing bad state from > context registers inherited from a malicious client. > > Fixes: 008ead6ef8f5 ("drm/i915/gt: Restore clear-residual mitigations for > Ivybridge, Baytrail") > Fixes: 09aa9e45863e ("drm/i915/gt: Restore clear-residual mitigations for > Ivybridge, Baytrail") > Testcase: igt/gem_ctx_isolation # ivb,vlv > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> > --- > drivers/gpu/drm/i915/gt/gen7_renderclear.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > index 56bdcdaa9a88..0490c29788d7 100644 > --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > @@ -390,6 +390,14 @@ static void emit_batch(struct i915_vma * const > vma, > &cb_kernel_ivb, > desc_count); > > + gen7_emit_pipeline_invalidate(&cmds); > + batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); > + batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); > + batch_add(&cmds, 0xffff0000); > + batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); > + batch_add(&cmds, 0xffff0000 | > PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); > + gen7_emit_pipeline_flush(&cmds); > + > gen7_emit_pipeline_invalidate(&cmds); > batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); > batch_add(&cmds, MI_NOOP); > -- > 2.20.1 Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Thanks, ~Akeem
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index 56bdcdaa9a88..0490c29788d7 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -390,6 +390,14 @@ static void emit_batch(struct i915_vma * const vma, &cb_kernel_ivb, desc_count); + gen7_emit_pipeline_invalidate(&cmds); + batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); + batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); + batch_add(&cmds, 0xffff0000); + batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); + batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + gen7_emit_pipeline_flush(&cmds); + gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA); batch_add(&cmds, MI_NOOP);
Since we do a bare context switch with no restore, the clear residual kernel runs on dirty state, and we must be careful to avoid executing bad state from context registers inherited from a malicious client. Fixes: 008ead6ef8f5 ("drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail") Fixes: 09aa9e45863e ("drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail") Testcase: igt/gem_ctx_isolation # ivb,vlv Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> --- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 8 ++++++++ 1 file changed, 8 insertions(+)