From patchwork Thu Jan 21 20:52:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12037713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55917C433E6 for ; Thu, 21 Jan 2021 20:53:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E345C23A61 for ; Thu, 21 Jan 2021 20:53:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E345C23A61 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 327A46E956; Thu, 21 Jan 2021 20:53:20 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC8246E956 for ; Thu, 21 Jan 2021 20:53:18 +0000 (UTC) IronPort-SDR: nTfboVUY9R9lep1b0woOonzMAiM+xpnMGE0vNKMN3aP0LTQjc+VBdrs0iJF5QE8GhUwpHTrYHf i3cpiDKjjPPw== X-IronPort-AV: E=McAfee;i="6000,8403,9871"; a="264159570" X-IronPort-AV: E=Sophos;i="5.79,365,1602572400"; d="scan'208";a="264159570" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2021 12:53:18 -0800 IronPort-SDR: c6IG3Ej+fdV0kyTDbbmo3+tG418wQpRXM/z2dHXqAQdsPi4t/VsC/sQoc94qPy/LrdwIN15tMa ksD7EzYhXfDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,365,1602572400"; d="scan'208";a="348044171" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 21 Jan 2021 12:53:15 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 21 Jan 2021 22:53:15 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Jan 2021 22:52:58 +0200 Message-Id: <20210121205302.24897-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210121205302.24897-1-ville.syrjala@linux.intel.com> References: <20210121205302.24897-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/8] drm/i915: Introduce skl_ddb_entry_for_slices() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Generalize icl_get_first_dbuf_slice_offset() into something that just gives us the start+end of the dbuf chunk covered by the specified slices as a standard ddb entry. Initial idea was to use it during readout as well, but we shall see. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++---------------------- 1 file changed, 18 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 100ec37ec483..4eb2d36ed108 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4035,25 +4035,23 @@ static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) INTEL_INFO(dev_priv)->num_supported_dbuf_slices; } -/* - * Calculate initial DBuf slice offset, based on slice size - * and mask(i.e if slice size is 1024 and second slice is enabled - * offset would be 1024) - */ -static unsigned int -icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask, - u32 slice_size, - u32 ddb_size) +static void +skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask, + struct skl_ddb_entry *ddb) { - unsigned int offset = 0; + int slice_size = intel_dbuf_slice_size(dev_priv); - if (!dbuf_slice_mask) - return 0; + if (!slice_mask) { + ddb->start = 0; + ddb->end = 0; + return; + } - offset = (ffs(dbuf_slice_mask) - 1) * slice_size; + ddb->start = (ffs(slice_mask) - 1) * slice_size; + ddb->end = fls(slice_mask) * slice_size; - WARN_ON(offset >= ddb_size); - return offset; + WARN_ON(ddb->start >= ddb->end); + WARN_ON(ddb->end > intel_dbuf_size(dev_priv)); } u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, @@ -4123,12 +4121,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, const struct intel_dbuf_state *old_dbuf_state = intel_atomic_get_old_dbuf_state(intel_state); u8 active_pipes = new_dbuf_state->active_pipes; - u16 ddb_size; + struct skl_ddb_entry ddb_slices; u32 ddb_range_size; u32 i; u32 dbuf_slice_mask; - u32 offset; - u32 slice_size; u32 total_slice_mask; u32 start, end; int ret; @@ -4141,9 +4137,6 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, return 0; } - ddb_size = intel_dbuf_size(dev_priv); - slice_size = intel_dbuf_slice_size(dev_priv); - /* * If the state doesn't change the active CRTC's or there is no * modeset request, then there's no need to recalculate; @@ -4169,20 +4162,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, */ dbuf_slice_mask = skl_compute_dbuf_slices(for_crtc, active_pipes); - /* - * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2 - * and slice size is 1024, the offset would be 1024 - */ - offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask, - slice_size, ddb_size); - - /* - * Figure out total size of allowed DBuf slices, which is basically - * a number of allowed slices for that pipe multiplied by slice size. - * Inside of this - * range ddb entries are still allocated in proportion to display width. - */ - ddb_range_size = hweight8(dbuf_slice_mask) * slice_size; + skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); + ddb_range_size = skl_ddb_entry_size(&ddb_slices); total_slice_mask = dbuf_slice_mask; for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { @@ -4239,8 +4220,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, start = ddb_range_size * weight_before_pipe / total_weight; end = ddb_range_size * (weight_before_pipe + pipe_weight) / total_weight; - alloc->start = offset + start; - alloc->end = offset + end; + alloc->start = ddb_slices.start + start; + alloc->end = ddb_slices.start + end; drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",