From patchwork Thu Jan 21 20:52:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12037715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9628FC433E0 for ; Thu, 21 Jan 2021 20:53:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B45423A61 for ; Thu, 21 Jan 2021 20:53:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5B45423A61 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 026FF6E957; Thu, 21 Jan 2021 20:53:27 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC4D56E957 for ; Thu, 21 Jan 2021 20:53:25 +0000 (UTC) IronPort-SDR: XxrCosai1h3Zz8CfAoKAp3LTqbSW9fxG1z0opa/SocO3JVtH2mYCsE3UiIBCOmHIKV7FWUmsq1 oP+R9Nkfk7RA== X-IronPort-AV: E=McAfee;i="6000,8403,9871"; a="243418060" X-IronPort-AV: E=Sophos;i="5.79,365,1602572400"; d="scan'208";a="243418060" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2021 12:53:21 -0800 IronPort-SDR: DawreQn7cI7yAxWhiS1pRVzwpt5TpSkAzf7h6KpQ8MAVxHKD1wC4xsVveZOVA8tbweHClsw0Fw +CJf13+hfZbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,365,1602572400"; d="scan'208";a="356655550" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga008.fm.intel.com with SMTP; 21 Jan 2021 12:53:18 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 21 Jan 2021 22:53:17 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Jan 2021 22:52:59 +0200 Message-Id: <20210121205302.24897-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210121205302.24897-1-ville.syrjala@linux.intel.com> References: <20210121205302.24897-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 5/8] drm/i915: Move pipe ddb entries into the dbuf state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The dbuf state will be where we collect all the inter-pipe dbuf allocation stuff. Start by moving the actual per-pipe ddb entries there. v2: Rebase Reviewed-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++------- .../drm/i915/display/intel_display_types.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 14 ++++--------- drivers/gpu/drm/i915/intel_pm.h | 4 ++++ 4 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b73bbe2383d0..1e4006535d31 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -12925,6 +12925,10 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state) static void skl_commit_modeset_enables(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + const struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; @@ -12939,7 +12943,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) /* ignore allocations for crtc's that have been turned off. */ if (!intel_crtc_needs_modeset(new_crtc_state)) { - entries[pipe] = old_crtc_state->wm.skl.ddb; + entries[pipe] = old_dbuf_state->ddb[pipe]; update_pipes |= BIT(pipe); } else { modeset_pipes |= BIT(pipe); @@ -12963,11 +12967,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + if (skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe], entries, I915_MAX_PIPES, pipe)) continue; - entries[pipe] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_dbuf_state->ddb[pipe]; update_pipes &= ~BIT(pipe); intel_update_crtc(state, crtc); @@ -12978,8 +12982,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) * then we need to wait for a vblank to pass for the * new ddb allocation to take effect. */ - if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, - &old_crtc_state->wm.skl.ddb) && + if (!skl_ddb_entry_equal(&new_dbuf_state->ddb[pipe], + &old_dbuf_state->ddb[pipe]) && (update_pipes | modeset_pipes)) intel_wait_for_vblank(dev_priv, pipe); } @@ -13031,10 +13035,11 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, I915_MAX_PIPES, pipe)); + drm_WARN_ON(&dev_priv->drm, + skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe], + entries, I915_MAX_PIPES, pipe)); - entries[pipe] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_dbuf_state->ddb[pipe]; update_pipes &= ~BIT(pipe); intel_update_crtc(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1a9243426a25..dce32cf436ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -796,7 +796,6 @@ struct intel_crtc_wm_state { struct skl_pipe_wm raw; /* gen9+ only needs 1-step wm programming */ struct skl_pipe_wm optimal; - struct skl_ddb_entry ddb; struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES]; } skl; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4eb2d36ed108..555d8f058f1f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4146,16 +4146,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, * grab _all_ crtc locks, including the one we currently hold. */ if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && - !dev_priv->wm.distrust_bios_wm) { - /* - * alloc may be cleared by clear_intel_crtc_state, - * copy from old state to be sure - * - * FIXME get rid of this mess - */ - *alloc = to_intel_crtc_state(for_crtc->base.state)->wm.skl.ddb; + !dev_priv->wm.distrust_bios_wm) return 0; - } /* * Get allowed DBuf slices for correspondent pipe and platform. @@ -4798,7 +4790,9 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; + struct intel_dbuf_state *dbuf_state = + intel_atomic_get_new_dbuf_state(state); + struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; u16 alloc_size, start = 0; u16 total[I915_MAX_PLANES] = {}; u16 uv_total[I915_MAX_PLANES] = {}; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 00910bc01407..724204bb8442 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -9,8 +9,10 @@ #include #include "display/intel_bw.h" +#include "display/intel_display.h" #include "display/intel_global_state.h" +#include "i915_drv.h" #include "i915_reg.h" struct drm_device; @@ -68,6 +70,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); struct intel_dbuf_state { struct intel_global_state base; + struct skl_ddb_entry ddb[I915_MAX_PIPES]; + u8 enabled_slices; u8 active_pipes; };