From patchwork Thu Jan 21 20:53:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12037717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F15AEC433DB for ; Thu, 21 Jan 2021 20:53:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8FD423A60 for ; Thu, 21 Jan 2021 20:53:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8FD423A60 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 235046E959; Thu, 21 Jan 2021 20:53:34 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D7E26E959 for ; Thu, 21 Jan 2021 20:53:32 +0000 (UTC) IronPort-SDR: ZZBytjhK6h3ECYn60/AkOaqxIRvnX/OB4iuE/0R2TwSi9Nexg76LL4bUX3G2YkroXxwHCgBnnp 3rk8nrfxs4Cg== X-IronPort-AV: E=McAfee;i="6000,8403,9871"; a="179493932" X-IronPort-AV: E=Sophos;i="5.79,365,1602572400"; d="scan'208";a="179493932" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2021 12:53:24 -0800 IronPort-SDR: 7tDJXC+06gRMRsok51iffYCM6gF8R8Djg1U6fQ7KDw3ci8/xEYyVf5ZMp37gWoPaHcieKsvmYt Zyr/5V4zkRiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,365,1602572400"; d="scan'208";a="385458885" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 21 Jan 2021 12:53:21 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 21 Jan 2021 22:53:21 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Jan 2021 22:53:00 +0200 Message-Id: <20210121205302.24897-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210121205302.24897-1-ville.syrjala@linux.intel.com> References: <20210121205302.24897-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 6/8] drm/i915: Extract intel_crtc_dbuf_weights() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the code to calculate the weights used to chunk up the dbuf between pipes. There's still extra stuff in there that shouldn't be there and must be moved out, but that requires a bit more state to be tracked in the dbuf state. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 145 ++++++++++++++++++++------------ 1 file changed, 89 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 555d8f058f1f..00a1d23663b9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4103,62 +4103,35 @@ static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_st static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes); -static int -skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *crtc_state, - const u64 total_data_rate, - struct skl_ddb_entry *alloc, /* out */ - int *num_active /* out */) +static int intel_crtc_dbuf_weights(struct intel_atomic_state *state, + struct intel_crtc *for_crtc, + unsigned int *weight_start, + unsigned int *weight_end, + unsigned int *weight_total) { - struct drm_atomic_state *state = crtc_state->uapi.state; - struct intel_atomic_state *intel_state = to_intel_atomic_state(state); - struct intel_crtc *for_crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_crtc *crtc; - unsigned int pipe_weight = 0, total_weight = 0, weight_before_pipe = 0; + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + u8 active_pipes = new_dbuf_state->active_pipes; enum pipe for_pipe = for_crtc->pipe; - struct intel_dbuf_state *new_dbuf_state = - intel_atomic_get_new_dbuf_state(intel_state); - const struct intel_dbuf_state *old_dbuf_state = - intel_atomic_get_old_dbuf_state(intel_state); - u8 active_pipes = new_dbuf_state->active_pipes; - struct skl_ddb_entry ddb_slices; - u32 ddb_range_size; - u32 i; - u32 dbuf_slice_mask; - u32 total_slice_mask; - u32 start, end; - int ret; - - *num_active = hweight8(active_pipes); - - if (!crtc_state->hw.active) { - alloc->start = 0; - alloc->end = 0; - return 0; - } - - /* - * If the state doesn't change the active CRTC's or there is no - * modeset request, then there's no need to recalculate; - * the existing pipe allocation limits should remain unchanged. - * Note that we're safe from racing commits since any racing commit - * that changes the active CRTC list or do modeset would need to - * grab _all_ crtc locks, including the one we currently hold. - */ - if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && - !dev_priv->wm.distrust_bios_wm) - return 0; + const struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + u8 dbuf_slice_mask; + u8 total_slice_mask; + int i, ret; /* * Get allowed DBuf slices for correspondent pipe and platform. */ dbuf_slice_mask = skl_compute_dbuf_slices(for_crtc, active_pipes); - - skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); - ddb_range_size = skl_ddb_entry_size(&ddb_slices); - total_slice_mask = dbuf_slice_mask; - for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { + + *weight_start = 0; + *weight_end = 0; + *weight_total = 0; + + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { enum pipe pipe = crtc->pipe; unsigned int weight; u8 pipe_dbuf_slice_mask; @@ -4189,12 +4162,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, continue; weight = intel_crtc_ddb_weight(crtc_state); - total_weight += weight; + *weight_total += weight; - if (pipe < for_pipe) - weight_before_pipe += weight; - else if (pipe == for_pipe) - pipe_weight = weight; + if (pipe < for_pipe) { + *weight_start += weight; + *weight_end += weight; + } else if (pipe == for_pipe) { + *weight_end += weight; + } } /* @@ -4209,15 +4184,73 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, return ret; } - start = ddb_range_size * weight_before_pipe / total_weight; - end = ddb_range_size * (weight_before_pipe + pipe_weight) / total_weight; + return 0; +} + +static int +skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, + const struct intel_crtc_state *crtc_state, + const u64 total_data_rate, + struct skl_ddb_entry *alloc, /* out */ + int *num_active /* out */) +{ + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + unsigned int weight_start, weight_end, weight_total; + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + u8 active_pipes = new_dbuf_state->active_pipes; + struct skl_ddb_entry ddb_slices; + u32 ddb_range_size; + u32 dbuf_slice_mask; + u32 start, end; + int ret; + + *num_active = hweight8(active_pipes); + + if (!crtc_state->hw.active) { + alloc->start = 0; + alloc->end = 0; + return 0; + } + + /* + * If the state doesn't change the active CRTC's or there is no + * modeset request, then there's no need to recalculate; + * the existing pipe allocation limits should remain unchanged. + * Note that we're safe from racing commits since any racing commit + * that changes the active CRTC list or do modeset would need to + * grab _all_ crtc locks, including the one we currently hold. + */ + if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes && + !dev_priv->wm.distrust_bios_wm) + return 0; + + /* + * Get allowed DBuf slices for correspondent pipe and platform. + */ + dbuf_slice_mask = skl_compute_dbuf_slices(crtc, active_pipes); + + skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices); + ddb_range_size = skl_ddb_entry_size(&ddb_slices); + + ret = intel_crtc_dbuf_weights(state, crtc, + &weight_start, &weight_end, &weight_total); + if (ret) + return ret; + + start = ddb_range_size * weight_start / weight_total; + end = ddb_range_size * weight_end / weight_total; alloc->start = ddb_slices.start + start; alloc->end = ddb_slices.start + end; drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n", - for_crtc->base.base.id, for_crtc->base.name, + crtc->base.base.id, crtc->base.name, dbuf_slice_mask, alloc->start, alloc->end, active_pipes); return 0;