From patchwork Thu Jan 28 19:24:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12054459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D91D9C433E0 for ; Thu, 28 Jan 2021 19:25:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9301364E4A for ; Thu, 28 Jan 2021 19:25:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9301364E4A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 810576E9F4; Thu, 28 Jan 2021 19:24:50 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 70E7C6E9D8 for ; Thu, 28 Jan 2021 19:24:39 +0000 (UTC) IronPort-SDR: 0L0J/ovw5DTTLE5rZIOh1pTTD8aL0QZq8oO5n59O+R/ZW2j7uyqiex+FoieXWCjdObo2sT1OtQ B466Mi0gBxQg== X-IronPort-AV: E=McAfee;i="6000,8403,9878"; a="244384039" X-IronPort-AV: E=Sophos;i="5.79,383,1602572400"; d="scan'208";a="244384039" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2021 11:24:38 -0800 IronPort-SDR: d6+bosadFjJ6An+mfKtijVL5jpRfJIA2aGyyAvog3j2qWiZDl4khvajY8f9go7rLWyaC8ki082 sXGUwabfGKxA== X-IronPort-AV: E=Sophos;i="5.79,383,1602572400"; d="scan'208";a="411110171" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2021 11:24:37 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Jan 2021 11:24:05 -0800 Message-Id: <20210128192413.1715802-11-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210128192413.1715802-1-matthew.d.roper@intel.com> References: <20210128192413.1715802-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/18] drm/i915/display13: Increase maximum watermark lines to 255 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display13 continues to use the same "skylake-style" watermark programming as other recent platforms. The only change to the watermark calculations compared to Display12 is that Display13 now allows a maximum of 255 lines vs the old limit of 31. Due to the larger possible lines value, the corresponding bits representing the value in PLANE_WM are also extended, so make sure we read/write enough bits. Let's also take this opportunity to switch over to the REG_FIELD notation. Bspec: 49325 Bspec: 50419 Cc: Ville Syrjälä Cc: Anshuman Gupta Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_reg.h | 3 +-- drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ec7bda22f4f3..03711ba05bf5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6424,8 +6424,7 @@ enum { #define _CUR_WM_TRANS_B_0 0x71168 #define PLANE_WM_EN (1 << 31) #define PLANE_WM_IGNORE_LINES (1 << 30) -#define PLANE_WM_LINES_SHIFT 14 -#define PLANE_WM_LINES_MASK 0x1f +#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14) #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */ #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6e9678bd0597..696ee3a1c28c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5160,6 +5160,14 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) return level > 0; } +static int skl_wm_max_lines(struct drm_i915_private *dev_priv) +{ + if (HAS_DISPLAY13(dev_priv)) + return 255; + else + return 31; +} + static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, int level, unsigned int latency, @@ -5268,7 +5276,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, if (!skl_wm_has_lines(dev_priv, level)) res_lines = 0; - if (res_lines > 31) { + if (res_lines > skl_wm_max_lines(dev_priv)) { /* reject it */ result->min_ddb_alloc = U16_MAX; return; @@ -5559,7 +5567,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, if (level->ignore_lines) val |= PLANE_WM_IGNORE_LINES; val |= level->plane_res_b; - val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; + val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->plane_res_l); intel_de_write_fw(dev_priv, reg, val); } @@ -6144,8 +6152,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level) level->plane_en = val & PLANE_WM_EN; level->ignore_lines = val & PLANE_WM_IGNORE_LINES; level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; - level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & - PLANE_WM_LINES_MASK; + level->plane_res_l = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); } void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,