From patchwork Thu Jan 28 19:24:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12054461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72CE3C433E9 for ; Thu, 28 Jan 2021 19:25:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3356164E46 for ; Thu, 28 Jan 2021 19:25:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3356164E46 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C714B6E9F5; Thu, 28 Jan 2021 19:24:50 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id C85A76E9E4 for ; Thu, 28 Jan 2021 19:24:39 +0000 (UTC) IronPort-SDR: wWG414NBZRZedDsH4cluPmMRsJX4kh2pzrZzkbJA35Pgv9Ef5KG8RliLZtBsWuJUy6rJ1ZwUZz J7RIuODcHcxQ== X-IronPort-AV: E=McAfee;i="6000,8403,9878"; a="167395490" X-IronPort-AV: E=Sophos;i="5.79,383,1602572400"; d="scan'208";a="167395490" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2021 11:24:38 -0800 IronPort-SDR: hqnImaWAfb6EFjHtR8Gl6gyr1Hn0mMtbVE1yNi+6opqtLQY6SII7wghyxg6XYzkFLGDanwqv/I Uqcf2Pp54vzA== X-IronPort-AV: E=Sophos;i="5.79,383,1602572400"; d="scan'208";a="411110180" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2021 11:24:37 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Jan 2021 11:24:07 -0800 Message-Id: <20210128192413.1715802-13-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210128192413.1715802-1-matthew.d.roper@intel.com> References: <20210128192413.1715802-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/18] drm/i915/display13: Add Wa_14011503030:d13 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Cc: Aditya Swarup Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 7dd12fe9137e..f5a268e81024 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5844,6 +5844,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR; intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val); } + + /* Wa_14011503030:d13 */ + if (HAS_DISPLAY13(dev_priv)) + intel_de_write(dev_priv, D13_DISPLAY_ERR_FATAL_MASK, ~0); } static void icl_display_core_uninit(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 03711ba05bf5..128b835c0adb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7776,6 +7776,8 @@ enum { #define GEN8_GT_BCS_IRQ (1 << 1) #define GEN8_GT_RCS_IRQ (1 << 0) +#define D13_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) + #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))