From patchwork Thu Jan 28 19:23:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12054447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49CBFC433E9 for ; Thu, 28 Jan 2021 19:24:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 007CD64E4A for ; Thu, 28 Jan 2021 19:24:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 007CD64E4A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 13EA16E9E5; Thu, 28 Jan 2021 19:24:49 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90C906E9D3 for ; Thu, 28 Jan 2021 19:24:38 +0000 (UTC) IronPort-SDR: hph6esJbf5WVOH0ltVMOvYwX0QSs8QyfelfEqNrCgUuQwUVRa5H/9sdb+ibvHzidY+E/sMDbx4 bb1G7JKFoyYQ== X-IronPort-AV: E=McAfee;i="6000,8403,9878"; a="244384032" X-IronPort-AV: E=Sophos;i="5.79,383,1602572400"; d="scan'208";a="244384032" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2021 11:24:37 -0800 IronPort-SDR: FEMhxdaptaZ1eoN9JaX7oQ+zdkTvAIcXeU58Dm3+M//jIGz+S1taQsriJws/B3BvcIIQ76vRO+ buZDOWVaR71Q== X-IronPort-AV: E=Sophos;i="5.79,383,1602572400"; d="scan'208";a="411110149" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2021 11:24:36 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Jan 2021 11:23:58 -0800 Message-Id: <20210128192413.1715802-4-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210128192413.1715802-1-matthew.d.roper@intel.com> References: <20210128192413.1715802-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display13 brings enhanced underrun recovery: the hardware can somewhat mitigate underruns by using an interpolated replacement pixel (soft underrun) or the previous pixel (hard underrun). Furthermore, underruns can now be caused downstream by the port, even if the pipe itself is operating properly. The interrupt register gives us extra bits to determine hard/soft underruns and whether the underrun was caused by the port, so let's pass the iir down to the underrun handler and print some more descriptive errors on Display13 platforms. The context of the underrun is also available via PIPE_STATUS, but since we have the same information in the IIR we don't have a need to read from there. PIPE_STATUS might be useful in debugfs in the future though. Bspec: 50335 Bspec: 50366 Cc: Lucas De Marchi Signed-off-by: Matt Roper --- .../drm/i915/display/intel_fifo_underrun.c | 55 ++++++++++++++++++- drivers/gpu/drm/i915/i915_irq.c | 14 ++++- drivers/gpu/drm/i915/i915_reg.h | 7 +++ 3 files changed, 73 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 813a4f7033e1..6c377f0fc1b3 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -359,6 +359,39 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, return old; } +static u32 +underrun_pipestat_mask(struct drm_i915_private *dev_priv) +{ + u32 mask = PIPE_FIFO_UNDERRUN_STATUS; + + if (HAS_DISPLAY13(dev_priv)) + mask |= PIPE_STAT_SOFT_UNDERRUN_D13 | + PIPE_STAT_HARD_UNDERRUN_D13 | + PIPE_STAT_PORT_UNDERRUN_D13; + + return mask; +} + +static const char * +pipe_underrun_reason(u32 pipestat_underruns) +{ + if (pipestat_underruns & PIPE_STAT_SOFT_UNDERRUN_D13) + /* + * Hardware used replacement/interpolated pixels at + * underrun locations. + */ + return "soft"; + else if (pipestat_underruns & PIPE_STAT_HARD_UNDERRUN_D13) + /* + * Hardware used previous pixel value at underrun + * locations. + */ + return "hard"; + else + /* Old platform or no extra soft/hard bit set */ + return "FIFO"; +} + /** * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt * @dev_priv: i915 device instance @@ -372,6 +405,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + u32 underruns = 0; /* We may be called too early in init, thanks BIOS! */ if (crtc == NULL) @@ -382,10 +416,27 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, crtc->cpu_fifo_underrun_disabled) return; + /* + * On Display13, we can find out whether an underrun is soft/hard from + * either the iir or PIPE_STAT, but we can only determine if underruns + * were due to downstream port logic from PIPE_STAT. + */ + underruns = intel_uncore_read(&dev_priv->uncore, ICL_PIPESTAT(pipe)) & + underrun_pipestat_mask(dev_priv); + intel_uncore_write(&dev_priv->uncore, ICL_PIPESTAT(pipe), underruns); + if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { trace_intel_cpu_fifo_underrun(dev_priv, pipe); - drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", - pipe_name(pipe)); + + if (underruns & PIPE_STAT_PORT_UNDERRUN_D13) + /* Underrun was caused downstream from the pipes */ + drm_err(&dev_priv->drm, "Port triggered a %s underrun on pipe %c\n", + pipe_underrun_reason(underruns), + pipe_name(pipe)); + else + drm_err(&dev_priv->drm, "CPU pipe %c %s underrun\n", + pipe_name(pipe), + pipe_underrun_reason(underruns)); } intel_fbc_handle_fifo_underrun_irq(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1bced71470a5..407b42706a14 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2389,6 +2389,18 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); } +static u32 +underrun_iir_mask(struct drm_i915_private *dev_priv) +{ + u32 mask = GEN8_PIPE_FIFO_UNDERRUN; + + if (HAS_DISPLAY13(dev_priv)) + mask |= D13_PIPE_SOFT_UNDERRUN | + D13_PIPE_HARD_UNDERRUN; + + return mask; +} + static irqreturn_t gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) { @@ -2497,7 +2509,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); - if (iir & GEN8_PIPE_FIFO_UNDERRUN) + if (iir & underrun_iir_mask(dev_priv)) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 10fd0e3af2d4..a57593f7d7b1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6039,14 +6039,18 @@ enum { #define PIPECONF_DITHER_TYPE_ST2 (2 << 2) #define PIPECONF_DITHER_TYPE_TEMP (3 << 2) #define _PIPEASTAT 0x70024 +#define _PIPEASTAT_ICL 0x70058 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) #define PIPE_CRC_ERROR_ENABLE (1UL << 29) #define PIPE_CRC_DONE_ENABLE (1UL << 28) +#define PIPE_STAT_SOFT_UNDERRUN_D13 (1UL << 28) #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) +#define PIPE_STAT_HARD_UNDERRUN_D13 (1UL << 27) #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) +#define PIPE_STAT_PORT_UNDERRUN_D13 (1UL << 26) #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) #define PIPE_DPST_EVENT_ENABLE (1UL << 23) @@ -6111,6 +6115,7 @@ enum { #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) +#define ICL_PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT_ICL) #define _PIPEAGCMAX 0x70010 #define _PIPEBGCMAX 0x71010 @@ -7789,6 +7794,8 @@ enum { #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) +#define D13_PIPE_SOFT_UNDERRUN (1 << 22) +#define D13_PIPE_HARD_UNDERRUN (1 << 21) #define GEN8_PIPE_CURSOR_FAULT (1 << 10) #define GEN8_PIPE_SPRITE_FAULT (1 << 9) #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)