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dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5818C6EE0E; Thu, 4 Feb 2021 18:10:59 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 671DB6EE0E for ; Thu, 4 Feb 2021 18:10:58 +0000 (UTC) IronPort-SDR: /uAWwLa3TYuzHzm7incOzawkcTCIBLfvcSxe4aM/MWxEn0L+fC/yJNvRjrxXafXglicPfz1S4s x+b8QHMMzs2g== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="160460340" X-IronPort-AV: E=Sophos;i="5.81,153,1610438400"; d="scan'208";a="160460340" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 10:10:57 -0800 IronPort-SDR: v8nQ4gxR9adoGQQXnxvplmt1/GmLP+94mBbEv9HNRjMSOlu/vypKfKiZXUoUEiFDG9mjh7BxNV mtu/sgmuCurw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,153,1610438400"; d="scan'208";a="397138931" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 04 Feb 2021 10:10:54 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Feb 2021 20:10:54 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Feb 2021 20:10:36 +0200 Message-Id: <20210204181048.24202-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210204181048.24202-1-ville.syrjala@linux.intel.com> References: <20210204181048.24202-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 02/14] drm/i915: Extract hsw_ddi_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}() and put it into the new encoder .{enable,disable}_clock() vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index fa032e377ebc..b8af7b7df12a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3426,9 +3426,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, intel_de_write(dev_priv, DPLL_CTRL2, val); - } else if (INTEL_GEN(dev_priv) < 9) { - intel_de_write(dev_priv, PORT_CLK_SEL(port), - hsw_pll_to_ddi_pll_sel(pll)); } mutex_unlock(&dev_priv->dpll.lock); @@ -3451,12 +3448,30 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (IS_GEN9_BC(dev_priv)) { intel_de_write(dev_priv, DPLL_CTRL2, intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); - } else if (INTEL_GEN(dev_priv) < 9) { - intel_de_write(dev_priv, PORT_CLK_SEL(port), - PORT_CLK_SEL_NONE); } } +static void hsw_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum port port = encoder->port; + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); +} + +static void hsw_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); +} + static void intel_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -5603,6 +5618,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + encoder->enable_clock = hsw_ddi_enable_clock; + encoder->disable_clock = hsw_ddi_disable_clock; + } + if (IS_DG1(dev_priv)) encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv))