From patchwork Thu Feb 4 18:10:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12068233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20DFBC433DB for ; Thu, 4 Feb 2021 18:11:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC26364F53 for ; Thu, 4 Feb 2021 18:11:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CC26364F53 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A6466EE10; Thu, 4 Feb 2021 18:11:04 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id B1DFC6EE10 for ; Thu, 4 Feb 2021 18:11:02 +0000 (UTC) IronPort-SDR: cSZ5c5OIt+rzQjsr+wt4jwpMnRFWTprzFTdBQK3l99mapVO094KBH61hrvLYXI/wb90gJtHtv/ jjtJdCJVqqfw== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="178737263" X-IronPort-AV: E=Sophos;i="5.81,153,1610438400"; d="scan'208";a="178737263" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 10:11:00 -0800 IronPort-SDR: sOR48PLQV8z078UikOujxLvuohpC14m9H4EYxExgng8DTdKFiSQC1i/2aP5+sDhdrl3+KPhCqk 3xIurDPOExdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,153,1610438400"; d="scan'208";a="356814051" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 04 Feb 2021 10:10:58 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Feb 2021 20:10:57 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Feb 2021 20:10:37 +0200 Message-Id: <20210204181048.24202-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210204181048.24202-1-ville.syrjala@linux.intel.com> References: <20210204181048.24202-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 03/14] drm/i915: Extract skl_ddi_{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the DDI clock routing clode for skl/derivatives into the new encoder vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 53 +++++++++++++++++------- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b8af7b7df12a..2a8e47a3a878 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3415,17 +3415,6 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, val = intel_de_read(dev_priv, DPCLKA_CFGCR0); val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); intel_de_write(dev_priv, DPCLKA_CFGCR0, val); - } else if (IS_GEN9_BC(dev_priv)) { - /* DDI -> PLL mapping */ - val = intel_de_read(dev_priv, DPLL_CTRL2); - - val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | - DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); - val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | - DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - - intel_de_write(dev_priv, DPLL_CTRL2, val); - } mutex_unlock(&dev_priv->dpll.lock); @@ -3445,12 +3434,43 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (IS_CANNONLAKE(dev_priv)) { intel_de_write(dev_priv, DPCLKA_CFGCR0, intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); - } else if (IS_GEN9_BC(dev_priv)) { - intel_de_write(dev_priv, DPLL_CTRL2, - intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); } } +static void skl_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum port port = encoder->port; + u32 val; + + if (drm_WARN_ON(&i915->drm, !pll)) + return; + + mutex_lock(&i915->dpll.lock); + + val = intel_de_read(i915, DPLL_CTRL2); + + val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | + DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); + val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | + DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); + + intel_de_write(i915, DPLL_CTRL2, val); + + mutex_unlock(&i915->dpll.lock); +} + +static void skl_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + intel_de_write(i915, DPLL_CTRL2, + intel_de_read(i915, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); +} + static void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -5618,7 +5638,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (IS_GEN9_BC(dev_priv)) { + encoder->enable_clock = skl_ddi_enable_clock; + encoder->disable_clock = skl_ddi_disable_clock; + } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { encoder->enable_clock = hsw_ddi_enable_clock; encoder->disable_clock = hsw_ddi_disable_clock; }