From patchwork Thu Feb 4 18:10:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12068237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43793C433DB for ; Thu, 4 Feb 2021 18:11:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0359364F4D for ; Thu, 4 Feb 2021 18:11:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0359364F4D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97E276EE19; Thu, 4 Feb 2021 18:11:09 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1D02F6EE15 for ; Thu, 4 Feb 2021 18:11:08 +0000 (UTC) IronPort-SDR: 7Ll+OUfAJWhSB5KVWRACzeEx1mWqeXBaJjLqUsLPlZIz+DPVZtrjqrhVWcMbnfvlihABCLCg57 NEZ3m51eVDcw== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="200292709" X-IronPort-AV: E=Sophos;i="5.81,153,1610438400"; d="scan'208";a="200292709" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 10:11:07 -0800 IronPort-SDR: 9AhWheJHfoyY3Kai/lAY/88BZmyJc7zKowfnXtMWN5Ae8wrMew+5ORJY5VqFFUvjNzGJT1ON6F iKPB3AbymneQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,153,1610438400"; d="scan'208";a="393303857" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 04 Feb 2021 10:11:04 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 04 Feb 2021 20:11:03 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Feb 2021 20:10:39 +0200 Message-Id: <20210204181048.24202-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210204181048.24202-1-ville.syrjala@linux.intel.com> References: <20210204181048.24202-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 05/14] drm/i915: Convert DG1 over to .{enable, disable}_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace dg1_{map,unmap}_plls_to_ports() with the appropriate encoder vfuncs. And let's relocate the disable function next to the enable function while at it. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++------------ 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9ea408ff254b..cbeb75d00013 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3127,8 +3127,8 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, return 0; } -static void dg1_map_plls_to_ports(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void dg1_ddi_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; @@ -3161,6 +3161,19 @@ static void dg1_map_plls_to_ports(struct intel_encoder *encoder, mutex_unlock(&dev_priv->dpll.lock); } +static void dg1_ddi_disable_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + + mutex_lock(&dev_priv->dpll.lock); + + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); + + mutex_unlock(&dev_priv->dpll.lock); +} + static void icl_map_plls_to_ports(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -3213,19 +3226,6 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, mutex_unlock(&dev_priv->dpll.lock); } -static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - - mutex_lock(&dev_priv->dpll.lock); - - intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, - DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); - - mutex_unlock(&dev_priv->dpll.lock); -} - static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -4007,9 +4007,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); - if (IS_DG1(dev_priv)) - dg1_map_plls_to_ports(encoder, crtc_state); - else if (INTEL_GEN(dev_priv) >= 11) + if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11) icl_map_plls_to_ports(encoder, crtc_state); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); @@ -4210,9 +4208,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, intel_ddi_post_disable_dp(state, encoder, old_crtc_state, old_conn_state); - if (IS_DG1(dev_priv)) - dg1_unmap_plls_to_ports(encoder); - else if (INTEL_GEN(dev_priv) >= 11) + if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11) icl_unmap_plls_to_ports(encoder); if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) @@ -5657,7 +5653,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (IS_CANNONLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + encoder->enable_clock = dg1_ddi_enable_clock; + encoder->disable_clock = dg1_ddi_disable_clock; + } else if (IS_CANNONLAKE(dev_priv)) { encoder->enable_clock = cnl_ddi_enable_clock; encoder->disable_clock = cnl_ddi_disable_clock; } else if (IS_GEN9_BC(dev_priv)) {