| Message ID | 20210205003310.282664-1-sagar.ghuge@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register | expand |
Quoting Sagar Ghuge (2021-02-05 00:33:10) > Adding this register to whitelist will allow UMD to toggle State Cache > Perf fix disable chicken bit. > > "If this bit is enabled, RCC uses BTP+BTI as address tag in its state > cache instead of BTI only" > > which will lead to dropping unnecessary render target flushes and stall > on scoreboard. The rest of the register looks safe to expose, and it passes our sanity checks that the register is local to the context and should not affect others. > Bspec: 11333 > Bspec: 45829 > > Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> The only missing piece of the puzzle that Joonas will require is a Link: to a reviewed userspace patch/MR to confirm the uABI. -Chris
On 2/5/21 5:33 AM, Chris Wilson wrote: > Quoting Sagar Ghuge (2021-02-05 00:33:10) >> Adding this register to whitelist will allow UMD to toggle State Cache >> Perf fix disable chicken bit. >> >> "If this bit is enabled, RCC uses BTP+BTI as address tag in its state >> cache instead of BTI only" >> >> which will lead to dropping unnecessary render target flushes and stall >> on scoreboard. > > The rest of the register looks safe to expose, and it passes our sanity > checks that the register is local to the context and should not affect > others. > >> Bspec: 11333 >> Bspec: 45829 >> >> Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> > > Acked-by: Chris Wilson <chris@chris-wilson.co.uk> > Thank you! > The only missing piece of the puzzle that Joonas will require is a > Link: to a reviewed userspace patch/MR to confirm the uABI. Link to MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8766 > -Chris >
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 53f7838bd3c4..318302475c28 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1473,6 +1473,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* WaEnableStateCacheRedirectToCS:icl */ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + /* WaAllowToDisableStateCachePerfFixFromUMD:icl */ + whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); + /* * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl * @@ -1533,6 +1536,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) /* Wa_1808121037:tgl */ whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); + /* WaAllowToDisableStateCachePerfFixFromUMD:tgl */ + whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); + /* Wa_1806527549:tgl */ whitelist_reg(w, HIZ_CHICKEN); break;
Adding this register to whitelist will allow UMD to toggle State Cache Perf fix disable chicken bit. "If this bit is enabled, RCC uses BTP+BTI as address tag in its state cache instead of BTI only" which will lead to dropping unnecessary render target flushes and stall on scoreboard. Bspec: 11333 Bspec: 45829 Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 1 file changed, 6 insertions(+)