diff mbox series

[v3,10/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()

Message ID 20210205214634.19341-11-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Clean up the DDI clock routing mess | expand

Commit Message

Ville Syrjälä Feb. 5, 2021, 9:46 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The other DDI .enable_clock() functions are trying to protect us
against pll==NULL. A bit tempted to throw out all the WARNs as
just unnecessary noise, but I guess they might have some use
when poking around the shared_dpll code (not sure it wouldn't
oops elsewhere though). So let's unify it all and sprinkle in
the missing WARNs for icl/dg1.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series


diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bd1eac282033..c98bdf456958 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1604,6 +1604,9 @@  static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;
 	 * If we fail this, something went very wrong: first 2 PLLs should be
 	 * used by first 2 phys and last 2 PLLs by last phys
@@ -1661,6 +1664,9 @@  static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 		sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+	if (drm_WARN_ON(&dev_priv->drm, !pll))
+		return;