From patchwork Fri Feb 5 21:46:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 12071003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88F32C433E0 for ; Fri, 5 Feb 2021 21:47:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 203C764FCF for ; Fri, 5 Feb 2021 21:47:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 203C764FCF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C21096F4EE; Fri, 5 Feb 2021 21:47:22 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EC686F4EC for ; Fri, 5 Feb 2021 21:47:21 +0000 (UTC) IronPort-SDR: uJlLmLqX4Y4qLcskKTkgibSCNAMNNDKw2L0w5OtrifUE1JRo4VZoWfBM+65o6rJYU5FMECoVH2 V7Edz3scMo4g== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="169167471" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="169167471" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:20 -0800 IronPort-SDR: mW5CUwRfkAYYKzsVGpJMlFuRrWtVSwIxbJOe+uNIZXIAkC28dZO+TGRBqBl7TglIO9vsb9jP27 y4d5FgpRGkIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="397616716" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 05 Feb 2021 13:47:18 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:17 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:29 +0200 Message-Id: <20210205214634.19341-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 10/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The other DDI .enable_clock() functions are trying to protect us against pll==NULL. A bit tempted to throw out all the WARNs as just unnecessary noise, but I guess they might have some use when poking around the shared_dpll code (not sure it wouldn't oops elsewhere though). So let's unify it all and sprinkle in the missing WARNs for icl/dg1. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bd1eac282033..c98bdf456958 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1604,6 +1604,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + if (drm_WARN_ON(&dev_priv->drm, !pll)) + return; + /* * If we fail this, something went very wrong: first 2 PLLs should be * used by first 2 phys and last 2 PLLs by last phys @@ -1661,6 +1664,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); } + if (drm_WARN_ON(&dev_priv->drm, !pll)) + return; + mutex_lock(&dev_priv->dpll.lock); /*