From patchwork Fri Feb 5 21:46:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12071011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C947C433E6 for ; Fri, 5 Feb 2021 21:47:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3787464FCE for ; Fri, 5 Feb 2021 21:47:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3787464FCE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBBC86F4F2; Fri, 5 Feb 2021 21:47:35 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C3396F4F2 for ; Fri, 5 Feb 2021 21:47:33 +0000 (UTC) IronPort-SDR: qCbkMgJu8amTGfCmsQkM8ibpRv3hjeL4Yxt/eWuRETMOeCQ8+uW0iwYKO1v7KcOkOJvt+/8zLW SkqdIT5R4YxA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="169167489" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="169167489" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 13:47:33 -0800 IronPort-SDR: frZ/VWhDHefHixuV6hSQOk3bhgDxKO1cDkJUEdpyZBDH12jUmSIgwidMcGoToO9tuOaFCncoLc Fi12LmJzUwPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="434612902" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 05 Feb 2021 13:47:31 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 05 Feb 2021 23:47:30 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 23:46:33 +0200 Message-Id: <20210205214634.19341-15-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210205214634.19341-1-ville.syrjala@linux.intel.com> References: <20210205214634.19341-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 14/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move icl_sanitize_encoder_pll_mapping() out from the middle of the .{enable,disable}_clock() functions. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 112 +++++++++++------------ 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 967871c2bf1e..d4b9410110fd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1715,62 +1715,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 port_mask; - bool ddi_clk_needed; - - /* - * In case of DP MST, we sanitize the primary encoder only, not the - * virtual ones. - */ - if (encoder->type == INTEL_OUTPUT_DP_MST) - return; - - if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { - u8 pipe_mask; - bool is_mst; - - intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); - /* - * In the unlikely case that BIOS enables DP in MST mode, just - * warn since our MST HW readout is incomplete. - */ - if (drm_WARN_ON(&dev_priv->drm, is_mst)) - return; - } - - port_mask = BIT(encoder->port); - ddi_clk_needed = encoder->base.crtc; - - if (encoder->type == INTEL_OUTPUT_DSI) { - struct intel_encoder *other_encoder; - - port_mask = intel_dsi_encoder_ports(encoder); - /* - * Sanity check that we haven't incorrectly registered another - * encoder using any of the ports of this DSI encoder. - */ - for_each_intel_encoder(&dev_priv->drm, other_encoder) { - if (other_encoder == encoder) - continue; - - if (drm_WARN_ON(&dev_priv->drm, - port_mask & BIT(other_encoder->port))) - return; - } - /* - * For DSI we keep the ddi clocks gated - * except during enable/disable sequence. - */ - ddi_clk_needed = false; - } - - if (!ddi_clk_needed && encoder->disable_clock) - encoder->disable_clock(encoder); -} - static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1931,6 +1875,62 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder) encoder->disable_clock(encoder); } +void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + u32 port_mask; + bool ddi_clk_needed; + + /* + * In case of DP MST, we sanitize the primary encoder only, not the + * virtual ones. + */ + if (encoder->type == INTEL_OUTPUT_DP_MST) + return; + + if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { + u8 pipe_mask; + bool is_mst; + + intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); + /* + * In the unlikely case that BIOS enables DP in MST mode, just + * warn since our MST HW readout is incomplete. + */ + if (drm_WARN_ON(&dev_priv->drm, is_mst)) + return; + } + + port_mask = BIT(encoder->port); + ddi_clk_needed = encoder->base.crtc; + + if (encoder->type == INTEL_OUTPUT_DSI) { + struct intel_encoder *other_encoder; + + port_mask = intel_dsi_encoder_ports(encoder); + /* + * Sanity check that we haven't incorrectly registered another + * encoder using any of the ports of this DSI encoder. + */ + for_each_intel_encoder(&dev_priv->drm, other_encoder) { + if (other_encoder == encoder) + continue; + + if (drm_WARN_ON(&dev_priv->drm, + port_mask & BIT(other_encoder->port))) + return; + } + /* + * For DSI we keep the ddi clocks gated + * except during enable/disable sequence. + */ + ddi_clk_needed = false; + } + + if (!ddi_clk_needed && encoder->disable_clock) + encoder->disable_clock(encoder); +} + static void icl_program_mg_dp_mode(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state)