From patchwork Sat Feb 6 02:09:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 12071565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20413C433E0 for ; Sat, 6 Feb 2021 02:10:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D8FCC6501C for ; Sat, 6 Feb 2021 02:10:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D8FCC6501C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3D1D6F542; Sat, 6 Feb 2021 02:10:38 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7389D6E3D3 for ; Sat, 6 Feb 2021 02:10:38 +0000 (UTC) IronPort-SDR: SnGjr+VJzcAOO3KgeckKrpyK+CYOsbvfA06IpS42jVEFPr7lZN3UTQpLrMeRxryUmR/G8ea3JV BI9bd3J9YbsA== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="181577457" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="181577457" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:38 -0800 IronPort-SDR: YXY0BiZr2M3o2wL2QqSyM2gn4+uZUJFuJfcgoR7lDYmszjhDutFVWhhZE72cbt8zdwkXKw6lJs M4q0UEC7fe0g== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="394141332" Received: from dceraolo-linux.fm.intel.com ([10.1.27.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 18:10:37 -0800 From: Daniele Ceraolo Spurio To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Feb 2021 18:09:16 -0800 Message-Id: <20210206020925.36729-6-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> References: <20210206020925.36729-1-daniele.ceraolospurio@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Z , Huang@freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set the KCR init during the boot time, which is required by hardware, to allow us doing further protection operation such as sending commands to GPU or TEE. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 +++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 4ddc8a71a3e7..950daee5b907 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -6,6 +6,24 @@ #include "gt/intel_context.h" #include "i915_drv.h" +/* KCR register definitions */ +#define KCR_INIT _MMIO(0x320f0) + +/* Setting KCR Init bit is required after system boot */ +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) + +static void kcr_pxp_enable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + +static void kcr_pxp_disable(struct intel_gt *gt) +{ + intel_uncore_write(gt->uncore, KCR_INIT, + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); +} + static int create_vcs_context(struct intel_pxp *pxp) { struct intel_gt *gt = pxp_to_gt(pxp); @@ -43,19 +61,28 @@ void intel_pxp_init(struct intel_pxp *pxp) if (!HAS_PXP(gt->i915)) return; + kcr_pxp_enable(gt); + ret = create_vcs_context(pxp); if (ret) - return; + goto out_kcr; drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n"); return; + +out_kcr: + kcr_pxp_disable(gt); } void intel_pxp_fini(struct intel_pxp *pxp) { + struct intel_gt *gt = pxp_to_gt(pxp); + if (!intel_pxp_is_enabled(pxp)) return; destroy_vcs_context(pxp); + + kcr_pxp_disable(gt); }