From patchwork Tue Feb 9 18:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12078769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD2E2C433E0 for ; Tue, 9 Feb 2021 18:13:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55D0C64EC9 for ; Tue, 9 Feb 2021 18:13:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 55D0C64EC9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CEF066EB8B; Tue, 9 Feb 2021 18:13:26 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 208B96E0F3 for ; Tue, 9 Feb 2021 18:13:23 +0000 (UTC) IronPort-SDR: DXokVzZHVFjPJ+7DZedqMrxz4CUcAwMwxGoSgiRwONy0A5mT8ix2DWknKlsye/mA+wwHjKRXU1 h34Dhd01nktg== X-IronPort-AV: E=McAfee;i="6000,8403,9890"; a="201014107" X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="201014107" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:22 -0800 IronPort-SDR: I5/9uAeU8d01b1MTVFxMQ554Dc2c2WM1ZL+n6T2LdBgW4G+RS8kqDvdkqjvD9QRuLp2RUdI/5y 94saE96d7bmA== X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="396324660" Received: from rmahmood-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.190.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:21 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Feb 2021 10:14:37 -0800 Message-Id: <20210209181439.215104-2-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209181439.215104-1-jose.souza@intel.com> References: <20210209181439.215104-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display: Only write to register in intel_psr2_program_trans_man_trk_ctl() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There is no support for two pipes one transcoder for PSR and if we had that the current code should not use cpu_transcoder. Also I can't see a scenario where crtc_state->enable_psr2_sel_fetch is set and PSR is not enabled and if by a bug it happens PSR HW will just ignore any value in set in PSR2_MAN_TRK_CTL. So dropping all the rest and keeping the same behavior that we have with intel_psr2_program_plane_sel_fetch(). Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1d3903612fcb..8ad9fcff3a12 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1226,23 +1226,13 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - struct intel_encoder *encoder; if (!HAS_PSR2_SEL_FETCH(dev_priv) || !crtc_state->enable_psr2_sel_fetch) return; - for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, - crtc_state->uapi.encoder_mask) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - - if (!intel_dp->psr.enabled) - continue; - - intel_de_write(dev_priv, - PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), - crtc_state->psr2_man_track_ctl); - } + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), + crtc_state->psr2_man_track_ctl); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,