diff mbox series

[v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume

Message ID 20210217180016.1937401-1-lyude@redhat.com (mailing list archive)
State New, archived
Headers show
Series [v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume | expand

Commit Message

Lyude Paul Feb. 17, 2021, 6 p.m. UTC
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>

For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.

v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
  workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
  functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
  more or less identical to spt_hpd_irq_setup() minus additionally enabling
  one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
  separate patch.
v4:
* Revert Wa_14010685332 system list in comments to how it was before
* Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
 1 file changed, 32 insertions(+), 17 deletions(-)

Comments

Imre Deak Feb. 17, 2021, 9:18 p.m. UTC | #1
On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> 
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
> 
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
>   workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
>   functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
>   more or less identical to spt_hpd_irq_setup() minus additionally enabling
>   one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
>   separate patch.
> v4:
> * Revert Wa_14010685332 system list in comments to how it was before
> * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>

Thanks, looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>

nit: cnp_display_clock_gating_wa() would be an even better name, could
be renamed while applying.

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
>  1 file changed, 32 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..9b56a8f81e1a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_uncore *uncore = &dev_priv->uncore;
> +
> +	/*
> +	 * Wa_14010685332:cnp/cmp,tgp,adp
> +	 * TODO: Clarify which platforms this applies to
> +	 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> +	 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> +	 */
> +	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> +	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> +				 SBCLK_RUN_REFCLK_DIS);
> +		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> +	}
> +}
> +
>  static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>  
>  	if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_reset(dev_priv);
> +
> +	cnp_display_clock_wa(dev_priv);
>  }
>  
>  static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
>  	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		GEN3_IRQ_RESET(uncore, SDE);
>  
> -	/* Wa_14010685332:cnp/cmp,tgp,adp */
> -	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> -	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> -	     INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> -		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> -				 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> -		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> -				 SBCLK_RUN_REFCLK_DIS, 0);
> -	}
> +	cnp_display_clock_wa(dev_priv);
>  }
>  
>  static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_uncore *uncore = &dev_priv->uncore;
> +	u32 mask = SDE_GMBUS_ICP;
> +
> +	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
>  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -	if (HAS_PCH_SPLIT(dev_priv))
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> +		icp_irq_postinstall(dev_priv);
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_postinstall(dev_priv);
>  
>  	gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>  	gen8_master_intr_enable(dev_priv->uncore.regs);
>  }
>  
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> -	struct intel_uncore *uncore = &dev_priv->uncore;
> -	u32 mask = SDE_GMBUS_ICP;
> -
> -	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>  
>  static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -- 
> 2.29.2
>
Lyude Paul Feb. 17, 2021, 9:19 p.m. UTC | #2
On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > 
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> > 
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> > v3:
> > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > * Add TODO item mentioning we need to clarify which platforms this
> >   workaround applies to
> > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> >   functionally equivalent on gen9 bc to the code v2 added
> > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> >   more or less identical to spt_hpd_irq_setup() minus additionally enabling
> >   one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> >   separate patch.
> > v4:
> > * Revert Wa_14010685332 system list in comments to how it was before
> > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
> 
> Thanks, looks ok to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> nit: cnp_display_clock_gating_wa() would be an even better name, could
> be renamed while applying.

Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
confirmation from the OEMs this is for that these patches still fix their issues
(since I unfortunately don't have any access to this hardware).

> 
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> >  1 file changed, 32 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..9b56a8f81e1a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> >         spin_unlock_irq(&dev_priv->irq_lock);
> >  }
> >  
> > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > +{
> > +       struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > +       /*
> > +        * Wa_14010685332:cnp/cmp,tgp,adp
> > +        * TODO: Clarify which platforms this applies to
> > +        * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > +        * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > +        */
> > +       if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > +           (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1)) {
> > +               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS,
> > +                                SBCLK_RUN_REFCLK_DIS);
> > +               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS, 0);
> > +       }
> > +}
> > +
> >  static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> >  {
> >         struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> >  
> >         if (HAS_PCH_SPLIT(dev_priv))
> >                 ibx_irq_reset(dev_priv);
> > +
> > +       cnp_display_clock_wa(dev_priv);
> >  }
> >  
> >  static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >                 GEN3_IRQ_RESET(uncore, SDE);
> >  
> > -       /* Wa_14010685332:cnp/cmp,tgp,adp */
> > -       if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > -           (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > -            INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > -               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > -                                SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > -               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > -                                SBCLK_RUN_REFCLK_DIS, 0);
> > -       }
> > +       cnp_display_clock_wa(dev_priv);
> >  }
> >  
> >  static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> >         }
> >  }
> >  
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > +       struct intel_uncore *uncore = &dev_priv->uncore;
> > +       u32 mask = SDE_GMBUS_ICP;
> > +
> > +       GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> >  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> >  {
> > -       if (HAS_PCH_SPLIT(dev_priv))
> > +       if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > +               icp_irq_postinstall(dev_priv);
> > +       else if (HAS_PCH_SPLIT(dev_priv))
> >                 ibx_irq_postinstall(dev_priv);
> >  
> >         gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> >         gen8_master_intr_enable(dev_priv->uncore.regs);
> >  }
> >  
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > -       struct intel_uncore *uncore = &dev_priv->uncore;
> > -       u32 mask = SDE_GMBUS_ICP;
> > -
> > -       GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >  
> >  static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> >  {
> > -- 
> > 2.29.2
> > 
>
Surendrakumar Upadhyay, TejaskumarX Feb. 18, 2021, 4:36 a.m. UTC | #3
> -----Original Message-----
> From: Lyude Paul <lyude@redhat.com>
> Sent: 18 February 2021 02:49
> To: Deak, Imre <imre.deak@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>; open list:DRM DRIVERS <dri-
> devel@lists.freedesktop.org>; open list <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
> 
> On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> > On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > > PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround
> > > - imre
> > > v3:
> > > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > > * Add TODO item mentioning we need to clarify which platforms this
> > >   workaround applies to
> > > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > >   functionally equivalent on gen9 bc to the code v2 added
> > > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks
> > > to be
> > >   more or less identical to spt_hpd_irq_setup() minus additionally
> > > enabling
> > >   one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > >   separate patch.
> > > v4:
> > > * Revert Wa_14010685332 system list in comments to how it was before
> > > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> >
> > Thanks, looks ok to me:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > nit: cnp_display_clock_gating_wa() would be an even better name, could
> > be renamed while applying.
> 
> Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
> confirmation from the OEMs this is for that these patches still fix their issues
> (since I unfortunately don't have any access to this hardware).

I can follow up with OEM to test or I can get it tested in my LAB, as I have RKL RVP (CML CPU) + TGP PCH with me.

> 
> >
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c | 49
> > > +++++++++++++++++++++------------
> > >  1 file changed, 32 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index 98145a7f28a4..9b56a8f81e1a
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > >         spin_unlock_irq(&dev_priv->irq_lock);
> > >  }
> > >
> > > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > > +{
> > > +       struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > +       /*
> > > +        * Wa_14010685332:cnp/cmp,tgp,adp
> > > +        * TODO: Clarify which platforms this applies to
> > > +        * TODO: Figure out if this workaround can be applied in the
> > > +s0ix
> > > suspend/resume handlers as
> > > +        * on earlier platforms and whether the workaround is also
> > > +needed
> > > for runtime suspend/resume
> > > +        */
> > > +       if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > +           (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > +INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1)) {
> > > +               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS,
> > > +                                SBCLK_RUN_REFCLK_DIS);
> > > +               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS, 0);
> > > +       }
> > > +}
> > > +
> > >  static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > >  {
> > >         struct intel_uncore *uncore = &dev_priv->uncore; @@ -3063,6
> > > +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > >
> > >         if (HAS_PCH_SPLIT(dev_priv))
> > >                 ibx_irq_reset(dev_priv);
> > > +
> > > +       cnp_display_clock_wa(dev_priv);
> > >  }
> > >
> > >  static void gen11_display_irq_reset(struct drm_i915_private
> > > *dev_priv) @@ -3104,15 +3124,7 @@ static void
> > > gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > >         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > >                 GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > -       /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > -       if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > -           (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > -            INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > -               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > -                                SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > -               intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > -                                SBCLK_RUN_REFCLK_DIS, 0);
> > > -       }
> > > +       cnp_display_clock_wa(dev_priv);
> > >  }
> > >
> > >  static void gen11_irq_reset(struct drm_i915_private *dev_priv) @@
> > > -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > >         }
> > >  }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > +       struct intel_uncore *uncore = &dev_priv->uncore;
> > > +       u32 mask = SDE_GMBUS_ICP;
> > > +
> > > +       GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); }
> > > +
> > >  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > >  {
> > > -       if (HAS_PCH_SPLIT(dev_priv))
> > > +       if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > +               icp_irq_postinstall(dev_priv);
> > > +       else if (HAS_PCH_SPLIT(dev_priv))
> > >                 ibx_irq_postinstall(dev_priv);
> > >
> > >         gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > >         gen8_master_intr_enable(dev_priv->uncore.regs);
> > >  }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > -       struct intel_uncore *uncore = &dev_priv->uncore;
> > > -       u32 mask = SDE_GMBUS_ICP;
> > > -
> > > -       GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); -}
> > >
> > >  static void gen11_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > >  {
> > > --
> > > 2.29.2
> > >
> >
> 
> --
> Sincerely,
>    Lyude Paul (she/her)
>    Software Engineer at Red Hat
> 
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to
> check on my status. I don't bite!
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..9b56a8f81e1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@  static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+
+	/*
+	 * Wa_14010685332:cnp/cmp,tgp,adp
+	 * TODO: Clarify which platforms this applies to
+	 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+	 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+	 */
+	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+				 SBCLK_RUN_REFCLK_DIS);
+		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+	}
+}
+
 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3063,6 +3081,8 @@  static void gen8_irq_reset(struct drm_i915_private *dev_priv)
 
 	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_reset(dev_priv);
+
+	cnp_display_clock_wa(dev_priv);
 }
 
 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3124,7 @@  static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		GEN3_IRQ_RESET(uncore, SDE);
 
-	/* Wa_14010685332:cnp/cmp,tgp,adp */
-	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
-	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
-	     INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
-		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
-				 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
-		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
-				 SBCLK_RUN_REFCLK_DIS, 0);
-	}
+	cnp_display_clock_wa(dev_priv);
 }
 
 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3776,19 @@  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+	u32 mask = SDE_GMBUS_ICP;
+
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_SPLIT(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		icp_irq_postinstall(dev_priv);
+	else if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev_priv);
 
 	gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3797,6 @@  static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 	gen8_master_intr_enable(dev_priv->uncore.regs);
 }
 
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
-	struct intel_uncore *uncore = &dev_priv->uncore;
-	u32 mask = SDE_GMBUS_ICP;
-
-	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 {