diff mbox series

drm/i915/display: Do not allow DC3CO if PSR SF is enabled

Message ID 20210222112415.1523930-1-gwan-gyeong.mun@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: Do not allow DC3CO if PSR SF is enabled | expand

Commit Message

Mun, Gwan-gyeong Feb. 22, 2021, 11:24 a.m. UTC
Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exitmachanism
has an issue with using of SelectiveFecth and PSR2 ManualTracking.
And as new GEN12+ platform like RKL, ADL-S/P don't have PSR2 HW tracking,
Selective Fetch wiil be enabled by default.
Therefore if the system enables PSR SelectiveFetch / PSR ManualTracking,
it does not allow DC3CO dc state, in that case.

When this DC3CO exit issue is addressed while PSR SF is enabled,
this restriction should be removed.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

Comments

José Roberto de Souza Feb. 22, 2021, 2:05 p.m. UTC | #1
On Mon, 2021-02-22 at 13:24 +0200, Gwan-gyeong Mun wrote:
> Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exitmachanism

typo and missing space between exit and mechanism

> has an issue with using of SelectiveFecth and PSR2 ManualTracking.

manual tracking.

> And as new GEN12+ platform like RKL, ADL-S/P don't have PSR2 HW tracking,
> Selective Fetch wiil be enabled by default.
> Therefore if the system enables PSR SelectiveFetch / PSR ManualTracking,
> it does not allow DC3CO dc state, in that case.
> 
> When this DC3CO exit issue is addressed while PSR SF is enabled,
> this restriction should be removed.
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f00c1750febd..b385b3f082f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -804,10 +804,12 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
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>  	mask = DC_STATE_EN_UPTO_DC5;
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> -	if (INTEL_GEN(dev_priv) >= 12)
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> -					  | DC_STATE_EN_DC9;
> -	else if (IS_GEN(dev_priv, 11))
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		/* DMC's DC3CO exit machanism has an issue with SelectiveFecth */
> +		if (!dev_priv->params.enable_psr2_sel_fetch)
> +			mask |=  DC_STATE_EN_DC3CO;
> +		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> +	} else if (IS_GEN(dev_priv, 11))
>  		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
>  	else if (IS_GEN9_LP(dev_priv))
>  		mask |= DC_STATE_EN_DC9;
> @@ -4588,10 +4590,15 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
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>  	switch (requested_dc) {
>  	case 4:
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
> +		/* DMC's DC3CO exit machanism has an issue with SelectiveFecth */
> +		if (!dev_priv->params.enable_psr2_sel_fetch)
> +			mask |=  DC_STATE_EN_DC3CO;
> +		mask |= DC_STATE_EN_UPTO_DC6;
>  		break;
>  	case 3:
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
> +		if (!dev_priv->params.enable_psr2_sel_fetch)
> +			mask |=  DC_STATE_EN_DC3CO;
> +		mask |= DC_STATE_EN_UPTO_DC5;
>  		break;

Doing this in the wrong place, would be much easier do it in tgl_dc3co_exitline_compute_config().

>  	case 2:
>  		mask |= DC_STATE_EN_UPTO_DC6;
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index f00c1750febd..b385b3f082f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -804,10 +804,12 @@  static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 
 	mask = DC_STATE_EN_UPTO_DC5;
 
-	if (INTEL_GEN(dev_priv) >= 12)
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
-					  | DC_STATE_EN_DC9;
-	else if (IS_GEN(dev_priv, 11))
+	if (INTEL_GEN(dev_priv) >= 12) {
+		/* DMC's DC3CO exit machanism has an issue with SelectiveFecth */
+		if (!dev_priv->params.enable_psr2_sel_fetch)
+			mask |=  DC_STATE_EN_DC3CO;
+		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
+	} else if (IS_GEN(dev_priv, 11))
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
 	else if (IS_GEN9_LP(dev_priv))
 		mask |= DC_STATE_EN_DC9;
@@ -4588,10 +4590,15 @@  static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 
 	switch (requested_dc) {
 	case 4:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+		/* DMC's DC3CO exit machanism has an issue with SelectiveFecth */
+		if (!dev_priv->params.enable_psr2_sel_fetch)
+			mask |=  DC_STATE_EN_DC3CO;
+		mask |= DC_STATE_EN_UPTO_DC6;
 		break;
 	case 3:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+		if (!dev_priv->params.enable_psr2_sel_fetch)
+			mask |=  DC_STATE_EN_DC3CO;
+		mask |= DC_STATE_EN_UPTO_DC5;
 		break;
 	case 2:
 		mask |= DC_STATE_EN_UPTO_DC6;