| Message ID | 20210224144214.24803-5-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Move DDI clock readout to encoder->get_config() | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Wednesday, February 24, 2021 4:42 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to > encoder->get_config() > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Move the *_get_ddi_pll() stuff into the encodet->get_config() hook. > There it neatly sits next to the matching .{enable,disable}_clock() functions. > > In order to avoid excessive boilerplate I changed the behaviour such that all > platforms now do the readout via crtc_state->port_dpll[]. > > ICL+ TC is still a bit special due to TBTPLL not having a functional > .get_freq(). Should probably change that by adopting the LCPLL approach, > but that would require a fairly substantial rework of the DPLL ID handling. So > leave it for later. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 6 +- > drivers/gpu/drm/i915/display/intel_crt.c | 2 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 321 +++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_ddi.h | 8 +- > drivers/gpu/drm/i915/display/intel_display.c | 219 ------------- > 5 files changed, 306 insertions(+), 250 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index 05d5709ae537..29fe4919392a 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1490,14 +1490,10 @@ static void > gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, static void > gen11_dsi_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) { > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); > > - /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ > - pipe_config->port_clock = intel_dpll_get_freq(i915, > - pipe_config->shared_dpll, > - &pipe_config- > >dpll_hw_state); > + intel_ddi_get_clock(encoder, pipe_config, > +icl_ddi_combo_get_pll(encoder)); > > pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; > if (intel_dsi->dual_link) > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c > b/drivers/gpu/drm/i915/display/intel_crt.c > index 91a8a42b4aa2..b03f74076f64 100644 > --- a/drivers/gpu/drm/i915/display/intel_crt.c > +++ b/drivers/gpu/drm/i915/display/intel_crt.c > @@ -142,7 +142,7 @@ static void hsw_crt_get_config(struct intel_encoder > *encoder, { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > - intel_ddi_get_config(encoder, pipe_config); > + hsw_ddi_get_config(encoder, pipe_config); > > pipe_config->hw.adjusted_mode.flags &= > ~(DRM_MODE_FLAG_PHSYNC | > DRM_MODE_FLAG_NHSYNC | > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index eeae78097a20..56f5f55a7c8f 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -304,25 +304,6 @@ static void ddi_dotclock_get(struct intel_crtc_state > *pipe_config) > pipe_config->hw.adjusted_mode.crtc_clock = dotclock; } > > -static void intel_ddi_clock_get(struct intel_encoder *encoder, > - struct intel_crtc_state *pipe_config) > -{ > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > - > - if (intel_phy_is_tc(dev_priv, phy) && > - intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == > - DPLL_ID_ICL_TBTPLL) > - pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, > - encoder- > >port); > - else > - pipe_config->port_clock = > - intel_dpll_get_freq(dev_priv, pipe_config- > >shared_dpll, > - &pipe_config->dpll_hw_state); > - > - ddi_dotclock_get(pipe_config); > -} > - > void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, > const struct drm_connector_state *conn_state) { > @@ -1608,6 +1589,17 @@ static void _cnl_ddi_disable_clock(struct > drm_i915_private *i915, i915_reg_t reg > mutex_unlock(&i915->dpll.lock); > } > > +static struct intel_shared_dpll * > +_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, > + u32 clk_sel_mask, u32 clk_sel_shift) { > + enum intel_dpll_id id; > + > + id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; > + > + return intel_get_shared_dpll_by_id(i915, id); } > + > static void adls_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1633,6 +1625,16 @@ static void adls_ddi_disable_clock(struct > intel_encoder *encoder) > ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); > } > > +static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum phy phy = intel_port_to_phy(i915, encoder->port); > + > + return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), > + > ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), > + ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); > +} > + > static void rkl_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1658,6 +1660,16 @@ static void rkl_ddi_disable_clock(struct > intel_encoder *encoder) > RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); > } > > +static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum phy phy = intel_port_to_phy(i915, encoder->port); > + > + return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, > + > RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), > + > RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); > +} > + > static void dg1_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1692,6 +1704,16 @@ static void dg1_ddi_disable_clock(struct > intel_encoder *encoder) > DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); > } > > +static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum phy phy = intel_port_to_phy(i915, encoder->port); > + > + return _cnl_ddi_get_pll(i915, DG1_DPCLKA_CFGCR0(phy), > + > DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), > + > DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); > +} > + > static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1717,6 +1739,16 @@ static void icl_ddi_combo_disable_clock(struct > intel_encoder *encoder) > ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); > } > > +struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum phy phy = intel_port_to_phy(i915, encoder->port); > + > + return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, > + > ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), > + > ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); > +} > + > static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1784,6 +1816,36 @@ static void icl_ddi_tc_disable_clock(struct > intel_encoder *encoder) > intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } > > +static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct > +intel_encoder *encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); > + enum port port = encoder->port; > + enum intel_dpll_id id; > + u32 tmp; > + > + tmp = intel_de_read(i915, DDI_CLK_SEL(port)); > + > + switch (tmp & DDI_CLK_SEL_MASK) { > + case DDI_CLK_SEL_TBT_162: > + case DDI_CLK_SEL_TBT_270: > + case DDI_CLK_SEL_TBT_540: > + case DDI_CLK_SEL_TBT_810: > + id = DPLL_ID_ICL_TBTPLL; > + break; > + case DDI_CLK_SEL_MG: > + id = icl_tc_port_to_pll_id(tc_port); > + break; > + default: > + MISSING_CASE(tmp); > + fallthrough; > + case DDI_CLK_SEL_NONE: > + return NULL; > + } > + > + return intel_get_shared_dpll_by_id(i915, id); } > + > static void cnl_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1809,6 +1871,39 @@ static void cnl_ddi_disable_clock(struct > intel_encoder *encoder) > DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } > > +static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum port port = encoder->port; > + > + return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0, > + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), > + DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)); > +} > + > +static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum intel_dpll_id id; > + > + switch (encoder->port) { > + case PORT_A: > + id = DPLL_ID_SKL_DPLL0; > + break; > + case PORT_B: > + id = DPLL_ID_SKL_DPLL1; > + break; > + case PORT_C: > + id = DPLL_ID_SKL_DPLL2; > + break; > + default: > + MISSING_CASE(encoder->port); > + return NULL; > + } > + > + return intel_get_shared_dpll_by_id(i915, id); } > + > static void skl_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -1843,6 +1938,28 @@ static void skl_ddi_disable_clock(struct > intel_encoder *encoder) > mutex_unlock(&i915->dpll.lock); > } > > +static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum port port = encoder->port; > + enum intel_dpll_id id; > + u32 tmp; > + > + tmp = intel_de_read(i915, DPLL_CTRL2); > + > + /* > + * FIXME Not sure if the override affects both > + * the PLL selection and the CLK_OFF bit. > + */ > + if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) > + return NULL; > + > + id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> > + DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); > + > + return intel_get_shared_dpll_by_id(i915, id); } > + > void hsw_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { @@ - > 1864,6 +1981,44 @@ void hsw_ddi_disable_clock(struct intel_encoder > *encoder) > intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } > > +static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder > +*encoder) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum port port = encoder->port; > + enum intel_dpll_id id; > + u32 tmp; > + > + tmp = intel_de_read(i915, PORT_CLK_SEL(port)); > + > + switch (tmp & PORT_CLK_SEL_MASK) { > + case PORT_CLK_SEL_WRPLL1: > + id = DPLL_ID_WRPLL1; > + break; > + case PORT_CLK_SEL_WRPLL2: > + id = DPLL_ID_WRPLL2; > + break; > + case PORT_CLK_SEL_SPLL: > + id = DPLL_ID_SPLL; > + break; > + case PORT_CLK_SEL_LCPLL_810: > + id = DPLL_ID_LCPLL_810; > + break; > + case PORT_CLK_SEL_LCPLL_1350: > + id = DPLL_ID_LCPLL_1350; > + break; > + case PORT_CLK_SEL_LCPLL_2700: > + id = DPLL_ID_LCPLL_2700; > + break; > + default: > + MISSING_CASE(tmp); > + fallthrough; > + case PORT_CLK_SEL_NONE: > + return NULL; > + } > + > + return intel_get_shared_dpll_by_id(i915, id); } > + > void intel_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { @@ - > 3293,8 +3448,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder > *encoder, > } > } > > -void intel_ddi_get_config(struct intel_encoder *encoder, > - struct intel_crtc_state *pipe_config) > +static void intel_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; > @@ -3341,7 +3496,7 @@ void intel_ddi_get_config(struct intel_encoder > *encoder, > } > > if (!pipe_config->bigjoiner_slave) > - intel_ddi_clock_get(encoder, pipe_config); > + ddi_dotclock_get(pipe_config); > > if (IS_GEN9_LP(dev_priv)) > pipe_config->lane_lat_optim_mask = > @@ -3371,6 +3526,114 @@ void intel_ddi_get_config(struct intel_encoder > *encoder, > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); } > > +void intel_ddi_get_clock(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state, > + struct intel_shared_dpll *pll) > +{ > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; > + struct icl_port_dpll *port_dpll = &crtc_state- > >icl_port_dplls[port_dpll_id]; > + bool pll_active; > + > + port_dpll->pll = pll; > + pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); > + drm_WARN_ON(&i915->drm, !pll_active); > + > + icl_set_active_port_dpll(crtc_state, port_dpll_id); > + > + crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state- > >shared_dpll, > + &crtc_state- > >dpll_hw_state); } > + > +static void adls_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void rkl_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void dg1_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void icl_ddi_combo_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, > icl_ddi_combo_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void icl_ddi_tc_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum icl_port_dpll_id port_dpll_id; > + struct icl_port_dpll *port_dpll; > + struct intel_shared_dpll *pll; > + bool pll_active; > + > + pll = icl_ddi_tc_get_pll(encoder); > + > + if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) > + port_dpll_id = ICL_PORT_DPLL_DEFAULT; > + else > + port_dpll_id = ICL_PORT_DPLL_MG_PHY; > + > + port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; > + > + port_dpll->pll = pll; > + pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); > + drm_WARN_ON(&i915->drm, !pll_active); > + > + icl_set_active_port_dpll(crtc_state, port_dpll_id); > + > + if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == > DPLL_ID_ICL_TBTPLL) > + crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder- > >port); > + else > + crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state- > >shared_dpll, > + &crtc_state- > >dpll_hw_state); > + > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void cnl_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void bxt_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +static void skl_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > +void hsw_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) { > + intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); > + intel_ddi_get_config(encoder, crtc_state); } > + > static void intel_ddi_sync_state(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > @@ -4057,7 +4320,6 @@ void intel_ddi_init(struct drm_i915_private > *dev_priv, enum port port) > encoder->post_disable = intel_ddi_post_disable; > encoder->update_pipe = intel_ddi_update_pipe; > encoder->get_hw_state = intel_ddi_get_hw_state; > - encoder->get_config = intel_ddi_get_config; > encoder->sync_state = intel_ddi_sync_state; > encoder->initial_fastset_check = intel_ddi_initial_fastset_check; > encoder->suspend = intel_dp_encoder_suspend; @@ -4073,37 > +4335,50 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum > port port) > if (IS_ALDERLAKE_S(dev_priv)) { > encoder->enable_clock = adls_ddi_enable_clock; > encoder->disable_clock = adls_ddi_disable_clock; > + encoder->get_config = adls_ddi_get_config; > } else if (IS_ROCKETLAKE(dev_priv)) { > encoder->enable_clock = rkl_ddi_enable_clock; > encoder->disable_clock = rkl_ddi_disable_clock; > + encoder->get_config = rkl_ddi_get_config; > } else if (IS_DG1(dev_priv)) { > encoder->enable_clock = dg1_ddi_enable_clock; > encoder->disable_clock = dg1_ddi_disable_clock; > + encoder->get_config = dg1_ddi_get_config; > } else if (IS_JSL_EHL(dev_priv)) { > if (intel_ddi_is_tc(dev_priv, port)) { > encoder->enable_clock = jsl_ddi_tc_enable_clock; > encoder->disable_clock = jsl_ddi_tc_disable_clock; > + encoder->get_config = icl_ddi_combo_get_config; > } else { > encoder->enable_clock = > icl_ddi_combo_enable_clock; > encoder->disable_clock = > icl_ddi_combo_disable_clock; > + encoder->get_config = icl_ddi_combo_get_config; > } > } else if (INTEL_GEN(dev_priv) >= 11) { > if (intel_ddi_is_tc(dev_priv, port)) { > encoder->enable_clock = icl_ddi_tc_enable_clock; > encoder->disable_clock = icl_ddi_tc_disable_clock; > + encoder->get_config = icl_ddi_tc_get_config; > } else { > encoder->enable_clock = > icl_ddi_combo_enable_clock; > encoder->disable_clock = > icl_ddi_combo_disable_clock; > + encoder->get_config = icl_ddi_combo_get_config; > } > } else if (IS_CANNONLAKE(dev_priv)) { > encoder->enable_clock = cnl_ddi_enable_clock; > encoder->disable_clock = cnl_ddi_disable_clock; > + encoder->get_config = cnl_ddi_get_config; > + } else if (IS_GEN9_LP(dev_priv)) { > + /* BXT/GLK have fixed PLL->port mapping */ > + encoder->get_config = bxt_ddi_get_config; > } else if (IS_GEN9_BC(dev_priv)) { > encoder->enable_clock = skl_ddi_enable_clock; > encoder->disable_clock = skl_ddi_disable_clock; > + encoder->get_config = skl_ddi_get_config; > } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { > encoder->enable_clock = hsw_ddi_enable_clock; > encoder->disable_clock = hsw_ddi_disable_clock; > + encoder->get_config = hsw_ddi_get_config; > } > > if (IS_DG1(dev_priv)) > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h > b/drivers/gpu/drm/i915/display/intel_ddi.h > index 4a0c1d5c85e7..0780c47efe0f 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.h > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h > @@ -30,9 +30,15 @@ void intel_ddi_fdi_post_disable(struct > intel_atomic_state *state, > const struct drm_connector_state > *old_conn_state); void intel_ddi_enable_clock(struct intel_encoder > *encoder, > const struct intel_crtc_state *crtc_state); > +void intel_ddi_get_clock(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state, > + struct intel_shared_dpll *pll); > void hsw_ddi_enable_clock(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); void > hsw_ddi_disable_clock(struct intel_encoder *encoder); > +void hsw_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state); struct > intel_shared_dpll > +*icl_ddi_combo_get_pll(struct intel_encoder *encoder); > void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -48,8 > +54,6 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state > *crtc_state); void intel_ddi_set_dp_msa(const struct intel_crtc_state > *crtc_state, > const struct drm_connector_state *conn_state); > bool intel_ddi_connector_get_hw_state(struct intel_connector > *intel_connector); -void intel_ddi_get_config(struct intel_encoder *encoder, > - struct intel_crtc_state *pipe_config); > void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, > bool state); > void intel_ddi_compute_min_voltage_level(struct drm_i915_private > *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 958c2a796bae..8b5cb814b679 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -6523,212 +6523,6 @@ static bool ilk_get_pipe_config(struct intel_crtc > *crtc, > return ret; > } > > -static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port > port, > - struct intel_crtc_state *pipe_config) > -{ > - enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; > - enum phy phy = intel_port_to_phy(dev_priv, port); > - struct icl_port_dpll *port_dpll; > - struct intel_shared_dpll *pll; > - enum intel_dpll_id id; > - bool pll_active; > - u32 clk_sel; > - > - clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & > DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > - id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy); > - > - if (WARN_ON(id > DPLL_ID_DG1_DPLL3)) > - return; > - > - pll = intel_get_shared_dpll_by_id(dev_priv, id); > - port_dpll = &pipe_config->icl_port_dplls[port_dpll_id]; > - > - port_dpll->pll = pll; > - pll_active = intel_dpll_get_hw_state(dev_priv, pll, > - &port_dpll->hw_state); > - drm_WARN_ON(&dev_priv->drm, !pll_active); > - > - icl_set_active_port_dpll(pipe_config, port_dpll_id); > -} > - > -static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port > port, > - struct intel_crtc_state *pipe_config) > -{ > - enum phy phy = intel_port_to_phy(dev_priv, port); > - enum icl_port_dpll_id port_dpll_id; > - struct icl_port_dpll *port_dpll; > - struct intel_shared_dpll *pll; > - enum intel_dpll_id id; > - bool pll_active; > - i915_reg_t reg; > - u32 temp; > - > - if (intel_phy_is_combo(dev_priv, phy)) { > - u32 mask, shift; > - > - if (IS_ALDERLAKE_S(dev_priv)) { > - reg = ADLS_DPCLKA_CFGCR(phy); > - mask = > ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); > - shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy); > - } else if (IS_ROCKETLAKE(dev_priv)) { > - reg = ICL_DPCLKA_CFGCR0; > - mask = > RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > - shift = > RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); > - } else { > - reg = ICL_DPCLKA_CFGCR0; > - mask = > ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > - shift = > ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); > - } > - > - temp = intel_de_read(dev_priv, reg) & mask; > - id = temp >> shift; > - port_dpll_id = ICL_PORT_DPLL_DEFAULT; > - } else if (intel_phy_is_tc(dev_priv, phy)) { > - u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & > DDI_CLK_SEL_MASK; > - > - if (clk_sel == DDI_CLK_SEL_MG) { > - id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, > - port)); > - port_dpll_id = ICL_PORT_DPLL_MG_PHY; > - } else { > - drm_WARN_ON(&dev_priv->drm, > - clk_sel < DDI_CLK_SEL_TBT_162); > - id = DPLL_ID_ICL_TBTPLL; > - port_dpll_id = ICL_PORT_DPLL_DEFAULT; > - } > - } else { > - drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); > - return; > - } > - > - pll = intel_get_shared_dpll_by_id(dev_priv, id); > - port_dpll = &pipe_config->icl_port_dplls[port_dpll_id]; > - > - port_dpll->pll = pll; > - pll_active = intel_dpll_get_hw_state(dev_priv, pll, > - &port_dpll->hw_state); > - drm_WARN_ON(&dev_priv->drm, !pll_active); > - > - icl_set_active_port_dpll(pipe_config, port_dpll_id); > -} > - > -static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port > port, > - struct intel_crtc_state *pipe_config) > -{ > - struct intel_shared_dpll *pll; > - enum intel_dpll_id id; > - bool pll_active; > - u32 temp; > - > - temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & > DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); > - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); > - > - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > > SKL_DPLL2)) > - return; > - > - pll = intel_get_shared_dpll_by_id(dev_priv, id); > - > - pipe_config->shared_dpll = pll; > - pll_active = intel_dpll_get_hw_state(dev_priv, pll, > - &pipe_config->dpll_hw_state); > - drm_WARN_ON(&dev_priv->drm, !pll_active); > -} > - > -static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, > - enum port port, > - struct intel_crtc_state *pipe_config) > -{ > - struct intel_shared_dpll *pll; > - enum intel_dpll_id id; > - bool pll_active; > - > - switch (port) { > - case PORT_A: > - id = DPLL_ID_SKL_DPLL0; > - break; > - case PORT_B: > - id = DPLL_ID_SKL_DPLL1; > - break; > - case PORT_C: > - id = DPLL_ID_SKL_DPLL2; > - break; > - default: > - drm_err(&dev_priv->drm, "Incorrect port type\n"); > - return; > - } > - > - pll = intel_get_shared_dpll_by_id(dev_priv, id); > - > - pipe_config->shared_dpll = pll; > - pll_active = intel_dpll_get_hw_state(dev_priv, pll, > - &pipe_config->dpll_hw_state); > - drm_WARN_ON(&dev_priv->drm, !pll_active); > -} > - > -static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port > port, > - struct intel_crtc_state *pipe_config) > -{ > - struct intel_shared_dpll *pll; > - enum intel_dpll_id id; > - bool pll_active; > - u32 temp; > - > - temp = intel_de_read(dev_priv, DPLL_CTRL2) & > DPLL_CTRL2_DDI_CLK_SEL_MASK(port); > - id = temp >> (port * 3 + 1); > - > - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > > SKL_DPLL3)) > - return; > - > - pll = intel_get_shared_dpll_by_id(dev_priv, id); > - > - pipe_config->shared_dpll = pll; > - pll_active = intel_dpll_get_hw_state(dev_priv, pll, > - &pipe_config->dpll_hw_state); > - drm_WARN_ON(&dev_priv->drm, !pll_active); > -} > - > -static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port > port, > - struct intel_crtc_state *pipe_config) > -{ > - struct intel_shared_dpll *pll; > - enum intel_dpll_id id; > - u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port)); > - bool pll_active; > - > - switch (ddi_pll_sel) { > - case PORT_CLK_SEL_WRPLL1: > - id = DPLL_ID_WRPLL1; > - break; > - case PORT_CLK_SEL_WRPLL2: > - id = DPLL_ID_WRPLL2; > - break; > - case PORT_CLK_SEL_SPLL: > - id = DPLL_ID_SPLL; > - break; > - case PORT_CLK_SEL_LCPLL_810: > - id = DPLL_ID_LCPLL_810; > - break; > - case PORT_CLK_SEL_LCPLL_1350: > - id = DPLL_ID_LCPLL_1350; > - break; > - case PORT_CLK_SEL_LCPLL_2700: > - id = DPLL_ID_LCPLL_2700; > - break; > - default: > - MISSING_CASE(ddi_pll_sel); > - fallthrough; > - case PORT_CLK_SEL_NONE: > - return; > - } > - > - pll = intel_get_shared_dpll_by_id(dev_priv, id); > - > - pipe_config->shared_dpll = pll; > - pll_active = intel_dpll_get_hw_state(dev_priv, pll, > - &pipe_config->dpll_hw_state); > - drm_WARN_ON(&dev_priv->drm, !pll_active); > -} > - > static bool hsw_get_transcoder_state(struct intel_crtc *crtc, > struct intel_crtc_state *pipe_config, > struct intel_display_power_domain_set > *power_domain_set) @@ -6885,19 +6679,6 @@ static void > hsw_get_ddi_port_state(struct intel_crtc *crtc, > port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); > } > > - if (IS_DG1(dev_priv)) > - dg1_get_ddi_pll(dev_priv, port, pipe_config); > - else if (INTEL_GEN(dev_priv) >= 11) > - icl_get_ddi_pll(dev_priv, port, pipe_config); > - else if (IS_CANNONLAKE(dev_priv)) > - cnl_get_ddi_pll(dev_priv, port, pipe_config); > - else if (IS_GEN9_LP(dev_priv)) > - bxt_get_ddi_pll(dev_priv, port, pipe_config); > - else if (IS_GEN9_BC(dev_priv)) > - skl_get_ddi_pll(dev_priv, port, pipe_config); > - else > - hsw_get_ddi_pll(dev_priv, port, pipe_config); > - > /* > * Haswell has only FDI/PCH transcoder A. It is which is connected to > * DDI E. So just check whether this pipe is wired to DDI E and > whether > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 05d5709ae537..29fe4919392a 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1490,14 +1490,10 @@ static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ - pipe_config->port_clock = intel_dpll_get_freq(i915, - pipe_config->shared_dpll, - &pipe_config->dpll_hw_state); + intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; if (intel_dsi->dual_link) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 91a8a42b4aa2..b03f74076f64 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -142,7 +142,7 @@ static void hsw_crt_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - intel_ddi_get_config(encoder, pipe_config); + hsw_ddi_get_config(encoder, pipe_config); pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index eeae78097a20..56f5f55a7c8f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -304,25 +304,6 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) pipe_config->hw.adjusted_mode.crtc_clock = dotclock; } -static void intel_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - - if (intel_phy_is_tc(dev_priv, phy) && - intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == - DPLL_ID_ICL_TBTPLL) - pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, - encoder->port); - else - pipe_config->port_clock = - intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll, - &pipe_config->dpll_hw_state); - - ddi_dotclock_get(pipe_config); -} - void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { @@ -1608,6 +1589,17 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg mutex_unlock(&i915->dpll.lock); } +static struct intel_shared_dpll * +_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, + u32 clk_sel_mask, u32 clk_sel_shift) +{ + enum intel_dpll_id id; + + id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; + + return intel_get_shared_dpll_by_id(i915, id); +} + static void adls_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1633,6 +1625,16 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } +static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), + ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), + ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); +} + static void rkl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1658,6 +1660,16 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder) RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } +static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, + RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); +} + static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1692,6 +1704,16 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder) DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } +static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + return _cnl_ddi_get_pll(i915, DG1_DPCLKA_CFGCR0(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); +} + static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1717,6 +1739,16 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } +struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(i915, encoder->port); + + return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); +} + static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1784,6 +1816,36 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } +static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); + enum port port = encoder->port; + enum intel_dpll_id id; + u32 tmp; + + tmp = intel_de_read(i915, DDI_CLK_SEL(port)); + + switch (tmp & DDI_CLK_SEL_MASK) { + case DDI_CLK_SEL_TBT_162: + case DDI_CLK_SEL_TBT_270: + case DDI_CLK_SEL_TBT_540: + case DDI_CLK_SEL_TBT_810: + id = DPLL_ID_ICL_TBTPLL; + break; + case DDI_CLK_SEL_MG: + id = icl_tc_port_to_pll_id(tc_port); + break; + default: + MISSING_CASE(tmp); + fallthrough; + case DDI_CLK_SEL_NONE: + return NULL; + } + + return intel_get_shared_dpll_by_id(i915, id); +} + static void cnl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1809,6 +1871,39 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder) DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } +static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + + return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0, + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), + DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)); +} + +static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum intel_dpll_id id; + + switch (encoder->port) { + case PORT_A: + id = DPLL_ID_SKL_DPLL0; + break; + case PORT_B: + id = DPLL_ID_SKL_DPLL1; + break; + case PORT_C: + id = DPLL_ID_SKL_DPLL2; + break; + default: + MISSING_CASE(encoder->port); + return NULL; + } + + return intel_get_shared_dpll_by_id(i915, id); +} + static void skl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1843,6 +1938,28 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder) mutex_unlock(&i915->dpll.lock); } +static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + enum intel_dpll_id id; + u32 tmp; + + tmp = intel_de_read(i915, DPLL_CTRL2); + + /* + * FIXME Not sure if the override affects both + * the PLL selection and the CLK_OFF bit. + */ + if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) + return NULL; + + id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> + DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); + + return intel_get_shared_dpll_by_id(i915, id); +} + void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1864,6 +1981,44 @@ void hsw_ddi_disable_clock(struct intel_encoder *encoder) intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } +static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum port port = encoder->port; + enum intel_dpll_id id; + u32 tmp; + + tmp = intel_de_read(i915, PORT_CLK_SEL(port)); + + switch (tmp & PORT_CLK_SEL_MASK) { + case PORT_CLK_SEL_WRPLL1: + id = DPLL_ID_WRPLL1; + break; + case PORT_CLK_SEL_WRPLL2: + id = DPLL_ID_WRPLL2; + break; + case PORT_CLK_SEL_SPLL: + id = DPLL_ID_SPLL; + break; + case PORT_CLK_SEL_LCPLL_810: + id = DPLL_ID_LCPLL_810; + break; + case PORT_CLK_SEL_LCPLL_1350: + id = DPLL_ID_LCPLL_1350; + break; + case PORT_CLK_SEL_LCPLL_2700: + id = DPLL_ID_LCPLL_2700; + break; + default: + MISSING_CASE(tmp); + fallthrough; + case PORT_CLK_SEL_NONE: + return NULL; + } + + return intel_get_shared_dpll_by_id(i915, id); +} + void intel_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -3293,8 +3448,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, } } -void intel_ddi_get_config(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) +static void intel_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; @@ -3341,7 +3496,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, } if (!pipe_config->bigjoiner_slave) - intel_ddi_clock_get(encoder, pipe_config); + ddi_dotclock_get(pipe_config); if (IS_GEN9_LP(dev_priv)) pipe_config->lane_lat_optim_mask = @@ -3371,6 +3526,114 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); } +void intel_ddi_get_clock(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct intel_shared_dpll *pll) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; + struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; + bool pll_active; + + port_dpll->pll = pll; + pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); + drm_WARN_ON(&i915->drm, !pll_active); + + icl_set_active_port_dpll(crtc_state, port_dpll_id); + + crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, + &crtc_state->dpll_hw_state); +} + +static void adls_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +static void rkl_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +static void dg1_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +static void icl_ddi_combo_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +static void icl_ddi_tc_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum icl_port_dpll_id port_dpll_id; + struct icl_port_dpll *port_dpll; + struct intel_shared_dpll *pll; + bool pll_active; + + pll = icl_ddi_tc_get_pll(encoder); + + if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) + port_dpll_id = ICL_PORT_DPLL_DEFAULT; + else + port_dpll_id = ICL_PORT_DPLL_MG_PHY; + + port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; + + port_dpll->pll = pll; + pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); + drm_WARN_ON(&i915->drm, !pll_active); + + icl_set_active_port_dpll(crtc_state, port_dpll_id); + + if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) + crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); + else + crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, + &crtc_state->dpll_hw_state); + + intel_ddi_get_config(encoder, crtc_state); +} + +static void cnl_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +static void bxt_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +static void skl_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + +void hsw_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); + intel_ddi_get_config(encoder, crtc_state); +} + static void intel_ddi_sync_state(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -4057,7 +4320,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->post_disable = intel_ddi_post_disable; encoder->update_pipe = intel_ddi_update_pipe; encoder->get_hw_state = intel_ddi_get_hw_state; - encoder->get_config = intel_ddi_get_config; encoder->sync_state = intel_ddi_sync_state; encoder->initial_fastset_check = intel_ddi_initial_fastset_check; encoder->suspend = intel_dp_encoder_suspend; @@ -4073,37 +4335,50 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) if (IS_ALDERLAKE_S(dev_priv)) { encoder->enable_clock = adls_ddi_enable_clock; encoder->disable_clock = adls_ddi_disable_clock; + encoder->get_config = adls_ddi_get_config; } else if (IS_ROCKETLAKE(dev_priv)) { encoder->enable_clock = rkl_ddi_enable_clock; encoder->disable_clock = rkl_ddi_disable_clock; + encoder->get_config = rkl_ddi_get_config; } else if (IS_DG1(dev_priv)) { encoder->enable_clock = dg1_ddi_enable_clock; encoder->disable_clock = dg1_ddi_disable_clock; + encoder->get_config = dg1_ddi_get_config; } else if (IS_JSL_EHL(dev_priv)) { if (intel_ddi_is_tc(dev_priv, port)) { encoder->enable_clock = jsl_ddi_tc_enable_clock; encoder->disable_clock = jsl_ddi_tc_disable_clock; + encoder->get_config = icl_ddi_combo_get_config; } else { encoder->enable_clock = icl_ddi_combo_enable_clock; encoder->disable_clock = icl_ddi_combo_disable_clock; + encoder->get_config = icl_ddi_combo_get_config; } } else if (INTEL_GEN(dev_priv) >= 11) { if (intel_ddi_is_tc(dev_priv, port)) { encoder->enable_clock = icl_ddi_tc_enable_clock; encoder->disable_clock = icl_ddi_tc_disable_clock; + encoder->get_config = icl_ddi_tc_get_config; } else { encoder->enable_clock = icl_ddi_combo_enable_clock; encoder->disable_clock = icl_ddi_combo_disable_clock; + encoder->get_config = icl_ddi_combo_get_config; } } else if (IS_CANNONLAKE(dev_priv)) { encoder->enable_clock = cnl_ddi_enable_clock; encoder->disable_clock = cnl_ddi_disable_clock; + encoder->get_config = cnl_ddi_get_config; + } else if (IS_GEN9_LP(dev_priv)) { + /* BXT/GLK have fixed PLL->port mapping */ + encoder->get_config = bxt_ddi_get_config; } else if (IS_GEN9_BC(dev_priv)) { encoder->enable_clock = skl_ddi_enable_clock; encoder->disable_clock = skl_ddi_disable_clock; + encoder->get_config = skl_ddi_get_config; } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { encoder->enable_clock = hsw_ddi_enable_clock; encoder->disable_clock = hsw_ddi_disable_clock; + encoder->get_config = hsw_ddi_get_config; } if (IS_DG1(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 4a0c1d5c85e7..0780c47efe0f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -30,9 +30,15 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state); void intel_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_ddi_get_clock(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct intel_shared_dpll *pll); void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void hsw_ddi_disable_clock(struct intel_encoder *encoder); +void hsw_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); +struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -48,8 +54,6 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); -void intel_ddi_get_config(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config); void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, bool state); void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 958c2a796bae..8b5cb814b679 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6523,212 +6523,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, return ret; } -static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, - struct intel_crtc_state *pipe_config) -{ - enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; - enum phy phy = intel_port_to_phy(dev_priv, port); - struct icl_port_dpll *port_dpll; - struct intel_shared_dpll *pll; - enum intel_dpll_id id; - bool pll_active; - u32 clk_sel; - - clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy); - - if (WARN_ON(id > DPLL_ID_DG1_DPLL3)) - return; - - pll = intel_get_shared_dpll_by_id(dev_priv, id); - port_dpll = &pipe_config->icl_port_dplls[port_dpll_id]; - - port_dpll->pll = pll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, - &port_dpll->hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); - - icl_set_active_port_dpll(pipe_config, port_dpll_id); -} - -static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, - struct intel_crtc_state *pipe_config) -{ - enum phy phy = intel_port_to_phy(dev_priv, port); - enum icl_port_dpll_id port_dpll_id; - struct icl_port_dpll *port_dpll; - struct intel_shared_dpll *pll; - enum intel_dpll_id id; - bool pll_active; - i915_reg_t reg; - u32 temp; - - if (intel_phy_is_combo(dev_priv, phy)) { - u32 mask, shift; - - if (IS_ALDERLAKE_S(dev_priv)) { - reg = ADLS_DPCLKA_CFGCR(phy); - mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); - shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy); - } else if (IS_ROCKETLAKE(dev_priv)) { - reg = ICL_DPCLKA_CFGCR0; - mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); - } else { - reg = ICL_DPCLKA_CFGCR0; - mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); - } - - temp = intel_de_read(dev_priv, reg) & mask; - id = temp >> shift; - port_dpll_id = ICL_PORT_DPLL_DEFAULT; - } else if (intel_phy_is_tc(dev_priv, phy)) { - u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; - - if (clk_sel == DDI_CLK_SEL_MG) { - id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, - port)); - port_dpll_id = ICL_PORT_DPLL_MG_PHY; - } else { - drm_WARN_ON(&dev_priv->drm, - clk_sel < DDI_CLK_SEL_TBT_162); - id = DPLL_ID_ICL_TBTPLL; - port_dpll_id = ICL_PORT_DPLL_DEFAULT; - } - } else { - drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); - return; - } - - pll = intel_get_shared_dpll_by_id(dev_priv, id); - port_dpll = &pipe_config->icl_port_dplls[port_dpll_id]; - - port_dpll->pll = pll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, - &port_dpll->hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); - - icl_set_active_port_dpll(pipe_config, port_dpll_id); -} - -static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, - struct intel_crtc_state *pipe_config) -{ - struct intel_shared_dpll *pll; - enum intel_dpll_id id; - bool pll_active; - u32 temp; - - temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); - - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)) - return; - - pll = intel_get_shared_dpll_by_id(dev_priv, id); - - pipe_config->shared_dpll = pll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, - &pipe_config->dpll_hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); -} - -static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, - enum port port, - struct intel_crtc_state *pipe_config) -{ - struct intel_shared_dpll *pll; - enum intel_dpll_id id; - bool pll_active; - - switch (port) { - case PORT_A: - id = DPLL_ID_SKL_DPLL0; - break; - case PORT_B: - id = DPLL_ID_SKL_DPLL1; - break; - case PORT_C: - id = DPLL_ID_SKL_DPLL2; - break; - default: - drm_err(&dev_priv->drm, "Incorrect port type\n"); - return; - } - - pll = intel_get_shared_dpll_by_id(dev_priv, id); - - pipe_config->shared_dpll = pll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, - &pipe_config->dpll_hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); -} - -static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, - struct intel_crtc_state *pipe_config) -{ - struct intel_shared_dpll *pll; - enum intel_dpll_id id; - bool pll_active; - u32 temp; - - temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); - id = temp >> (port * 3 + 1); - - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)) - return; - - pll = intel_get_shared_dpll_by_id(dev_priv, id); - - pipe_config->shared_dpll = pll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, - &pipe_config->dpll_hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); -} - -static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, - struct intel_crtc_state *pipe_config) -{ - struct intel_shared_dpll *pll; - enum intel_dpll_id id; - u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port)); - bool pll_active; - - switch (ddi_pll_sel) { - case PORT_CLK_SEL_WRPLL1: - id = DPLL_ID_WRPLL1; - break; - case PORT_CLK_SEL_WRPLL2: - id = DPLL_ID_WRPLL2; - break; - case PORT_CLK_SEL_SPLL: - id = DPLL_ID_SPLL; - break; - case PORT_CLK_SEL_LCPLL_810: - id = DPLL_ID_LCPLL_810; - break; - case PORT_CLK_SEL_LCPLL_1350: - id = DPLL_ID_LCPLL_1350; - break; - case PORT_CLK_SEL_LCPLL_2700: - id = DPLL_ID_LCPLL_2700; - break; - default: - MISSING_CASE(ddi_pll_sel); - fallthrough; - case PORT_CLK_SEL_NONE: - return; - } - - pll = intel_get_shared_dpll_by_id(dev_priv, id); - - pipe_config->shared_dpll = pll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, - &pipe_config->dpll_hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); -} - static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) @@ -6885,19 +6679,6 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); } - if (IS_DG1(dev_priv)) - dg1_get_ddi_pll(dev_priv, port, pipe_config); - else if (INTEL_GEN(dev_priv) >= 11) - icl_get_ddi_pll(dev_priv, port, pipe_config); - else if (IS_CANNONLAKE(dev_priv)) - cnl_get_ddi_pll(dev_priv, port, pipe_config); - else if (IS_GEN9_LP(dev_priv)) - bxt_get_ddi_pll(dev_priv, port, pipe_config); - else if (IS_GEN9_BC(dev_priv)) - skl_get_ddi_pll(dev_priv, port, pipe_config); - else - hsw_get_ddi_pll(dev_priv, port, pipe_config); - /* * Haswell has only FDI/PCH transcoder A. It is which is connected to * DDI E. So just check whether this pipe is wired to DDI E and whether