From patchwork Fri Mar 5 20:04:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 12119425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F95C433E0 for ; Fri, 5 Mar 2021 20:05:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D90C6509A for ; Fri, 5 Mar 2021 20:05:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D90C6509A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E0C46EC45; Fri, 5 Mar 2021 20:05:05 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA2246EC45 for ; Fri, 5 Mar 2021 20:05:03 +0000 (UTC) IronPort-SDR: hQS9JRU0tdFvTCgQzJv9KUdTJjkEW66xkV9NicPcU7Y/HmEKwD+bnFFtArBpPbfAnXQApnIqQg daN++j8nHVpg== X-IronPort-AV: E=McAfee;i="6000,8403,9914"; a="184349578" X-IronPort-AV: E=Sophos;i="5.81,226,1610438400"; d="scan'208";a="184349578" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2021 12:05:03 -0800 IronPort-SDR: Y13ViZNX2EFIy4Svyx0AlpTZaRuYhRL/7XUvKlzGeKr3y2VaLteB6lG/GO+eo7qwAwYa07PZtZ XSKjoOtceL9w== X-IronPort-AV: E=Sophos;i="5.81,226,1610438400"; d="scan'208";a="408478102" Received: from srobinso-mobl.ger.corp.intel.com (HELO helsinki.intel.com) ([10.214.242.78]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2021 12:05:01 -0800 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Mar 2021 22:04:50 +0200 Message-Id: <20210305200451.397875-2-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210305200451.397875-1-gwan-gyeong.mun@intel.com> References: <20210305200451.397875-1-gwan-gyeong.mun@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It removes intel_crtc_state from function argument of intel_psr_enable_source() in order to use intel_psr_enable_source() without intel_crtc_state on other psr internal functions. And we can get cpu_trancoder from intel_psr, therefore we don't need to pass intel_crtc_state to this function. Cc: José Roberto de Souza Signed-off-by: Gwan-gyeong Mun Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9c25a701943a..ce7ce82d6f1b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -896,11 +896,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) intel_dp->psr.active = true; } -static void intel_psr_enable_source(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static void intel_psr_enable_source(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 mask; /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ @@ -1008,7 +1007,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, &intel_dp->psr.vsc); intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc); intel_psr_enable_sink(intel_dp); - intel_psr_enable_source(intel_dp, crtc_state); + intel_psr_enable_source(intel_dp); intel_dp->psr.enabled = true; intel_psr_activate(intel_dp);