From patchwork Mon Mar 8 06:27:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Winkler, Tomas" X-Patchwork-Id: 12121573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE908C433E6 for ; Mon, 8 Mar 2021 06:28:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2BDE651EF for ; Mon, 8 Mar 2021 06:28:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2BDE651EF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3584D6E804; Mon, 8 Mar 2021 06:28:29 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBDEB6E81A for ; Mon, 8 Mar 2021 06:28:27 +0000 (UTC) IronPort-SDR: sz2DfoeABRruntOG2uYE/eNQgCuGCvp/1JeaY6VcJKUQErpOar4PKq/DygPkWQEfe5JTGP6g/Z FYUrd4k5b8mQ== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="249354852" X-IronPort-AV: E=Sophos;i="5.81,231,1610438400"; d="scan'208";a="249354852" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2021 22:28:27 -0800 IronPort-SDR: YaG8UgBBFu3NnNGKqnVf1pXZTiJ2qyM1F5GI6CRelJS0GMi0M8bsrHPqJ3LUv0VRLKKCePaqrN j2DsjElyoiHA== X-IronPort-AV: E=Sophos;i="5.81,231,1610438400"; d="scan'208";a="409181995" Received: from twinkler-lnx.jer.intel.com ([10.12.91.138]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2021 22:28:23 -0800 From: Tomas Winkler To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi Date: Mon, 8 Mar 2021 08:27:45 +0200 Message-Id: <20210308062748.208017-8-tomas.winkler@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210308062748.208017-1-tomas.winkler@intel.com> References: <20210308062748.208017-1-tomas.winkler@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH 07/10 v2] drm/i915/spi: mtd: implement access handlers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Usyskin , intel-gfx@lists.freedesktop.org, Lucas De Marchi , linux-mtd@lists.infradead.org, Tomas Winkler , Vitaly Lubart Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement mtd read, erase, and write handlers. For erase operation address and size should be 4K aligned. For write operation address and size has to be 4bytes aligned. Cc: Rodrigo Vivi Cc: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Vitaly Lubart --- V2: 1. Rebase drivers/gpu/drm/i915/spi/i915_spi.c | 138 ++++++++++++++++++++++++++-- 1 file changed, 131 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/spi/i915_spi.c b/drivers/gpu/drm/i915/spi/i915_spi.c index bdf58e14fd6b..1e8a40339e6d 100644 --- a/drivers/gpu/drm/i915/spi/i915_spi.c +++ b/drivers/gpu/drm/i915/spi/i915_spi.c @@ -173,7 +173,6 @@ static int i915_spi_is_valid(struct i915_spi *spi) return 0; } -__maybe_unused static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from) { unsigned int i; @@ -188,7 +187,6 @@ static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from) return i; } -__maybe_unused static ssize_t spi_write(struct i915_spi *spi, u8 region, loff_t to, size_t len, const unsigned char *buf) { @@ -219,7 +217,6 @@ static ssize_t spi_write(struct i915_spi *spi, u8 region, return len; } -__maybe_unused static ssize_t spi_read(struct i915_spi *spi, u8 region, loff_t from, size_t len, unsigned char *buf) { @@ -261,7 +258,6 @@ static ssize_t spi_read(struct i915_spi *spi, u8 region, return len; } -__maybe_unused static ssize_t spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr) { @@ -350,7 +346,63 @@ static int i915_spi_init(struct i915_spi *spi, struct device *device) static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info) { - dev_err(&mtd->dev, "erasing %lld %lld\n", info->addr, info->len); + struct i915_spi *spi; + unsigned int idx; + u8 region; + u64 addr; + ssize_t bytes; + loff_t from; + size_t len; + size_t total_len; + + if (!mtd || !info) + return -EINVAL; + + spi = mtd->priv; + + if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) { + dev_err(&mtd->dev, "unaligned erase %llx %llx\n", + info->addr, info->len); + info->fail_addr = MTD_FAIL_ADDR_UNKNOWN; + return -EINVAL; + } + + total_len = info->len; + addr = info->addr; + + while (total_len > 0) { + if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) { + dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len); + info->fail_addr = addr; + return -ERANGE; + } + + idx = spi_get_region(spi, addr); + if (idx >= spi->nregions) { + dev_err(&mtd->dev, "out of range"); + info->fail_addr = MTD_FAIL_ADDR_UNKNOWN; + return -ERANGE; + } + + from = addr - spi->regions[idx].offset; + region = spi->regions[idx].id; + len = total_len; + if (len > spi->regions[idx].size - from) + len = spi->regions[idx].size - from; + + dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n", + region, spi->regions[idx].name, from, len); + + bytes = spi_erase(spi, region, from, len, &info->fail_addr); + if (bytes < 0) { + dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes); + info->fail_addr += spi->regions[idx].offset; + return bytes; + } + + addr += len; + total_len -= len; + } return 0; } @@ -358,7 +410,43 @@ static int i915_spi_erase(struct mtd_info *mtd, struct erase_info *info) static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { - dev_err(&mtd->dev, "read %lld %zd\n", from, len); + struct i915_spi *spi; + ssize_t ret; + unsigned int idx; + u8 region; + + if (!mtd) + return -EINVAL; + + spi = mtd->priv; + + if (!IS_ALIGNED(from, sizeof(u32))) { + dev_err(&mtd->dev, "unaligned read %lld %zd\n", from, len); + return -EINVAL; + } + + idx = spi_get_region(spi, from); + + dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n", + spi->regions[idx].id, spi->regions[idx].name, from, len); + + if (idx >= spi->nregions) { + dev_err(&mtd->dev, "out of ragnge"); + return -ERANGE; + } + + from -= spi->regions[idx].offset; + region = spi->regions[idx].id; + if (len > spi->regions[idx].size - from) + len = spi->regions[idx].size - from; + + ret = spi_read(spi, region, from, len, buf); + if (ret < 0) { + dev_dbg(&mtd->dev, "read failed with %zd\n", ret); + return ret; + } + + *retlen = ret; return 0; } @@ -366,7 +454,43 @@ static int i915_spi_read(struct mtd_info *mtd, loff_t from, size_t len, static int i915_spi_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { - dev_err(&mtd->dev, "writing %lld %zd\n", to, len); + struct i915_spi *spi; + ssize_t ret; + unsigned int idx; + u8 region; + + if (!mtd) + return -EINVAL; + + spi = mtd->priv; + + if (!(IS_ALIGNED(len, 4) && IS_ALIGNED(to, 4))) { + dev_err(&mtd->dev, "unaligned write %lld %zd\n", to, len); + return -EINVAL; + } + + idx = spi_get_region(spi, to); + + dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n", + spi->regions[idx].id, spi->regions[idx].name, to, len); + + if (idx >= spi->nregions) { + dev_err(&mtd->dev, "out of range"); + return -ERANGE; + } + + to -= spi->regions[idx].offset; + region = spi->regions[idx].id; + if (len > spi->regions[idx].size - to) + len = spi->regions[idx].size - to; + + ret = spi_write(spi, region, to, len, buf); + if (ret < 0) { + dev_dbg(&mtd->dev, "write failed with %zd\n", ret); + return ret; + } + + *retlen = ret; return 0; }