From patchwork Thu Mar 11 22:36:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12133123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A4D4C433DB for ; Thu, 11 Mar 2021 22:37:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F7BA64F26 for ; Thu, 11 Mar 2021 22:37:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6F7BA64F26 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC8E86EEAB; Thu, 11 Mar 2021 22:36:55 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id AFE2C6EE9B for ; Thu, 11 Mar 2021 22:36:50 +0000 (UTC) IronPort-SDR: TCPTHZpFT7JbYLgxUkzVofz654xiZDoPlFaUqB//Lz5Obm7iD4+Flz3IJWsIDbDBidT7GoMFP2 c393MBcwg/ug== X-IronPort-AV: E=McAfee;i="6000,8403,9920"; a="250116463" X-IronPort-AV: E=Sophos;i="5.81,241,1610438400"; d="scan'208";a="250116463" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2021 14:36:48 -0800 IronPort-SDR: TkAe0bIz0vQGCMiXzF76slYhyO+vqghkYxlMzeFtLA9Ps/sRTTYx1o0Ho818Agsv4cakPCnOfj UdXfSOBOCedg== X-IronPort-AV: E=Sophos;i="5.81,241,1610438400"; d="scan'208";a="438852808" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2021 14:36:46 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Mar 2021 14:36:29 -0800 Message-Id: <20210311223632.3191939-54-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210311223632.3191939-1-matthew.d.roper@intel.com> References: <20210311223632.3191939-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 53/56] drm/i915/display/adl_p: Implement Wa_22011320316 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Implementation details are in the HSD 22011320316, requiring CD clock to be at least 307MHz to make DC states to work. Cc: Matt Roper Cc: Anusha Srivatsa Signed-off-by: José Roberto de Souza Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 21 ++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 42c462cae032..09e55ae3c471 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1257,6 +1257,21 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { + { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, + + { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, + + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, + {} +}; + static const struct intel_cdclk_vals adlp_cdclk_table[] = { { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, @@ -2836,7 +2851,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; - dev_priv->cdclk.table = adlp_cdclk_table; + /* Wa_22011320316:adlp[a0] */ + if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0)) + dev_priv->cdclk.table = adlp_a_step_cdclk_table; + else + dev_priv->cdclk.table = adlp_cdclk_table; } else if (IS_ROCKETLAKE(dev_priv)) { dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 10b99f9e380b..6ab27566b570 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1612,6 +1612,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) tgl_stepping_get(p)->gt_stepping >= (since) && \ tgl_stepping_get(p)->gt_stepping <= (until)) +#define ADLP_REVID_A0 0x0 +#define ADLP_REVID_B0 0x4 +#define ADLP_REVID_C0 0x8 + +#define IS_ADLP_REVID(p, since, until) \ + (IS_ALDERLAKE_P(p) && IS_REVID(p, since, until)) + #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))