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[1/3] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again

Message ID 20210319143021.21823-1-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/3] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again | expand

Commit Message

Ville Syrjälä March 19, 2021, 2:30 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We've defined C0DRB3/C0DRB3 as 16 bit registers, so access them
as such.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e891552611d5..e889a76c85c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -642,8 +642,8 @@  static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 		 * banks of memory are paired and unswizzled on the
 		 * uneven portion, so leave that as unknown.
 		 */
-		if (intel_uncore_read(uncore, C0DRB3) ==
-		    intel_uncore_read(uncore, C1DRB3)) {
+		if (intel_uncore_read16(uncore, C0DRB3) ==
+		    intel_uncore_read16(uncore, C1DRB3)) {
 			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 			swizzle_y = I915_BIT_6_SWIZZLE_9;
 		}