From patchwork Mon Mar 22 20:58:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12156159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3F2AC433E0 for ; Mon, 22 Mar 2021 20:56:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8BDB26187E for ; Mon, 22 Mar 2021 20:56:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8BDB26187E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 609C589F71; Mon, 22 Mar 2021 20:56:07 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id B883989F71 for ; Mon, 22 Mar 2021 20:56:05 +0000 (UTC) IronPort-SDR: RhO5J/lYI+ingDKOvjnjGvViL8JGoPtgzqMymp9r7z5qO4y9bga03EmYh6GWV42MAx0dpqk7sY 2apDSsYw6Q1w== X-IronPort-AV: E=McAfee;i="6000,8403,9931"; a="251700666" X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="251700666" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 13:56:04 -0700 IronPort-SDR: V/WcXXZxkC0y99WrXrH/nGKzdmgYGfx86Cq1umDNS3Fv+3ZR2HBkvgl8cemLlipLFbauk3Eint cutejH213X3w== X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="414643340" Received: from doothoux-mobl3.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.31.75]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 13:56:02 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Mar 2021 13:58:04 -0700 Message-Id: <20210322205805.62205-2-jose.souza@intel.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210322205805.62205-1-jose.souza@intel.com> References: <20210322205805.62205-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915: Do not set any power wells when there is no display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Power wells are only part of display block and not necessary when running a headless driver. Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Reviewed-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 7e0eaa872350..e6a3b3e6b1f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4673,7 +4673,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { + if (!HAS_DISPLAY(dev_priv)) { + power_domains->power_well_count = 0; + err = 0; + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) {