Message ID | 20210325180720.401410-15-matthew.d.roper@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
Return-Path: <SRS0=Bn5a=IX=lists.freedesktop.org=intel-gfx-bounces@kernel.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED50AC433DB for <intel-gfx@archiver.kernel.org>; Thu, 25 Mar 2021 18:07:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B8FD61A24 for <intel-gfx@archiver.kernel.org>; Thu, 25 Mar 2021 18:07:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B8FD61A24 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 705C06EE20; Thu, 25 Mar 2021 18:07:32 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBC356EE03 for <intel-gfx@lists.freedesktop.org>; Thu, 25 Mar 2021 18:07:30 +0000 (UTC) IronPort-SDR: 0bldFFCUXoSqHyWn/q7OH0PHqry1/lUF5vIvUo7lxQnmsEqGaeyN6Kowkmn6YAeOc/hUCuhgPz 7zcRo81T6aSw== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="178112526" X-IronPort-AV: E=Sophos;i="5.81,278,1610438400"; d="scan'208";a="178112526" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 11:07:29 -0700 IronPort-SDR: EMVWhREaUVkZOX5RI+TI5nsv0bh70M2iiBYQYwCYQNaGlkgRtyejynrljDPvqsyRCQCR0OJbuY +F1NCnt7siGg== X-IronPort-AV: E=Sophos;i="5.81,278,1610438400"; d="scan'208";a="453176582" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2021 11:07:29 -0700 From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Mar 2021 11:06:44 -0700 Message-Id: <20210325180720.401410-15-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210325180720.401410-1-matthew.d.roper@intel.com> References: <20210325180720.401410-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 14/50] drm/i915: Get slice height before computing rc params X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development <intel-gfx.lists.freedesktop.org> List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe> List-Archive: <https://lists.freedesktop.org/archives/intel-gfx> List-Post: <mailto:intel-gfx@lists.freedesktop.org> List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help> List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/intel-gfx>, <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe> Cc: me@freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org> |
Series |
Introduce Alder Lake-P
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expand
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diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index af2c47e50884..57a1868475ae 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1190,10 +1190,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; - ret = intel_dsc_compute_params(encoder, crtc_state); - if (ret) - return ret; - /* * Slice Height of 8 works for all currently available panels. So start * with that if pic_height is an integral multiple of 8. Eventually add @@ -1206,6 +1202,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, else vdsc_cfg->slice_height = 2; + ret = intel_dsc_compute_params(encoder, crtc_state); + if (ret) + return ret; + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;