From patchwork Tue Apr 13 05:09:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 12199241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F725C43460 for ; Tue, 13 Apr 2021 05:11:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD5BC611CE for ; Tue, 13 Apr 2021 05:11:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BD5BC611CE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B9316E214; Tue, 13 Apr 2021 05:10:54 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46FEB6E140 for ; Tue, 13 Apr 2021 05:10:48 +0000 (UTC) IronPort-SDR: 4Map2n5GU/iUrGaTlyWFQfi+5tmfqS5AX8JR7luM8I1d4dP0/mzsrIvS9c8rkL9PgQvmY+xzMw g8d/CM9isZ7Q== X-IronPort-AV: E=McAfee;i="6200,9189,9952"; a="194371984" X-IronPort-AV: E=Sophos;i="5.82,218,1613462400"; d="scan'208";a="194371984" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 22:10:46 -0700 IronPort-SDR: Pa2tM5KzQOfifISbI0SJEJm/P1WT1sSVAher5KDbObgorguKkOR+dKQqK8ekOLG5BtIzW9Cip4 axuYj1Oyf9jA== X-IronPort-AV: E=Sophos;i="5.82,218,1613462400"; d="scan'208";a="460450751" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.202]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 22:10:44 -0700 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Mon, 12 Apr 2021 22:09:54 -0700 Message-Id: <20210413051002.92589-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210413051002.92589-1-lucas.demarchi@intel.com> References: <20210413051002.92589-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 04/12] drm/i915: add macros for graphics and media versions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Like it was done in commit 01eb15c9165e ("drm/i915: Add DISPLAY_VER() and related macros") add the correspondent macros for graphics and media. Going forward we will prefer checking the versions for the specific IPs (graphics, media and display) rather than grouping everything under a "gen" version. For consistency and to make the maintenance easier, it'd be preferred not to mix the *GEN* macros with the new ones. For older platforms we can simply consider that the previous "gen" number will extend to all 3 IPs. Then we can start replacing its use in the driver. Right now this replacement is not done and only the infrastructure is put in place. We also leave gen and gen_mask inside struct intel_device_info while it's still being used throughout the code. v2: Repurpose IS_{GRAPHICS,MEDIA}_VER() macros to work with a range Signed-off-by: Lucas De Marchi Reviewed-by: José Roberto de Souza Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++++++++- drivers/gpu/drm/i915/i915_pci.c | 7 ++++++- drivers/gpu/drm/i915/intel_device_info.h | 3 +++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 907c66efb469..cb59eb0f6c5b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1234,9 +1234,22 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) -#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) +/* + * Deprecated: this will be replaced by individual IP checks: + * GRAPHICS_VER(), MEDIA_VER and DISPLAY_VER() + */ +#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) + +#define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver) +#define IS_GRAPHICS_VER(i915, from, until) \ + (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) + +#define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver) +#define IS_MEDIA_VER(i915, from, until) \ + (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) + #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver) #define IS_DISPLAY_VER(i915, from, until) \ (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index ce5cbeaf036d..97ab73276334 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -36,7 +36,12 @@ #include "i915_selftest.h" #define PLATFORM(x) .platform = (x) -#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), .display.ver = (x) +#define GEN(x) \ + .gen_mask = BIT((x) - 1), \ + .gen = (x), \ + .graphics_ver = (x), \ + .media_ver = (x), \ + .display.ver = (x) #define I845_PIPE_OFFSETS \ .pipe_offsets = { \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index b16c75927a12..405883a8cc84 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -162,6 +162,9 @@ enum intel_ppgtt_type { struct intel_device_info { u16 gen_mask; + u8 graphics_ver; + u8 media_ver; + u8 gen; u8 gt; /* GT number, 0 if undefined */ intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */