diff mbox series

[RFC,19/28] drm/i915: Replace arithmetic INTEL_GEN checks with the IS_GEN macro

Message ID 20210414115028.168504-20-tvrtko.ursulin@linux.intel.com (mailing list archive)
State New
Headers show
Series Old platform/gen kconfig options series | expand

Commit Message

Tvrtko Ursulin April 14, 2021, 11:50 a.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This moves the checks to at compile time which enables the compiler
to drop a lot of code in cases where whole platform sets are disabled.

Coccinelle transformation:

@@
expression p;
constant g;
@@
(
-INTEL_GEN(p) >= g
+IS_GEN(p, g, GEN_FOREVER)
|
-INTEL_GEN(p) <= g
+IS_GEN(p, GEN_FOREVER, g)
)

@@
expression p;
@@
(
-INTEL_GEN(p) > 2
+IS_GEN(p, 3, GEN_FOREVER)
|
-INTEL_GEN(p) > 3
+IS_GEN(p, 4, GEN_FOREVER)
|
-INTEL_GEN(p) > 4
+IS_GEN(p, 5, GEN_FOREVER)
|
-INTEL_GEN(p) > 5
+IS_GEN(p, 6, GEN_FOREVER)
|
-INTEL_GEN(p) > 6
+IS_GEN(p, 7, GEN_FOREVER)
|
-INTEL_GEN(p) > 7
+IS_GEN(p, 8, GEN_FOREVER)
|
-INTEL_GEN(p) > 8
+IS_GEN(p, 9, GEN_FOREVER)
|
-INTEL_GEN(p) > 9
+IS_GEN(p, 10, GEN_FOREVER)
|
-INTEL_GEN(p) > 10
+IS_GEN(p, 11, GEN_FOREVER)
|
-INTEL_GEN(p) > 11
+IS_GEN(p, 12, GEN_FOREVER)
|
-INTEL_GEN(p) < 2
+IS_GEN(p, GEN_FOREVER, 1)
|
-INTEL_GEN(p) < 3
+IS_GEN(p, GEN_FOREVER, 2)
|
-INTEL_GEN(p) < 4
+IS_GEN(p, GEN_FOREVER, 3)
|
-INTEL_GEN(p) < 5
+IS_GEN(p, GEN_FOREVER, 4)
|
-INTEL_GEN(p) < 6
+IS_GEN(p, GEN_FOREVER, 5)
|
-INTEL_GEN(p) < 7
+IS_GEN(p, GEN_FOREVER, 6)
|
-INTEL_GEN(p) < 8
+IS_GEN(p, GEN_FOREVER, 7)
|
-INTEL_GEN(p) < 9
+IS_GEN(p, GEN_FOREVER, 8)
|
-INTEL_GEN(p) < 10
+IS_GEN(p, GEN_FOREVER, 9)
|
-INTEL_GEN(p) < 11
+IS_GEN(p, GEN_FOREVER, 10)
)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c           |  86 ++++----
 drivers/gpu/drm/i915/i915_drv.c               |  16 +-
 drivers/gpu/drm/i915/i915_drv.h               |  14 +-
 drivers/gpu/drm/i915/i915_gem.c               |  18 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c    |   2 +-
 drivers/gpu/drm/i915/i915_gem_fence_reg.c     |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  30 +--
 drivers/gpu/drm/i915/i915_gem_request.c       |   2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c        |   6 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c        |   8 +-
 drivers/gpu/drm/i915/i915_gpu_error.c         |  40 ++--
 drivers/gpu/drm/i915/i915_irq.c               |  58 +++---
 drivers/gpu/drm/i915/i915_perf.c              |   2 +-
 drivers/gpu/drm/i915/i915_pmu.c               |   6 +-
 drivers/gpu/drm/i915/i915_reg.h               |   4 +-
 drivers/gpu/drm/i915/i915_suspend.c           |  12 +-
 drivers/gpu/drm/i915/i915_sysfs.c             |   2 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c     |   2 +-
 drivers/gpu/drm/i915/intel_audio.c            |   2 +-
 drivers/gpu/drm/i915/intel_cdclk.c            |   8 +-
 drivers/gpu/drm/i915/intel_color.c            |   2 +-
 drivers/gpu/drm/i915/intel_crt.c              |   6 +-
 drivers/gpu/drm/i915/intel_ddi.c              |  10 +-
 drivers/gpu/drm/i915/intel_device_info.c      |  14 +-
 drivers/gpu/drm/i915/intel_display.c          | 194 +++++++++---------
 drivers/gpu/drm/i915/intel_dp.c               |  28 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c         |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c        |  22 +-
 drivers/gpu/drm/i915/intel_fbc.c              |  30 +--
 drivers/gpu/drm/i915/intel_fifo_underrun.c    |   2 +-
 drivers/gpu/drm/i915/intel_hangcheck.c        |   2 +-
 drivers/gpu/drm/i915/intel_hdcp.c             |   2 +-
 drivers/gpu/drm/i915/intel_hdmi.c             |  10 +-
 drivers/gpu/drm/i915/intel_lrc.c              |   6 +-
 drivers/gpu/drm/i915/intel_lvds.c             |  10 +-
 drivers/gpu/drm/i915/intel_mocs.c             |   2 +-
 drivers/gpu/drm/i915/intel_overlay.c          |   2 +-
 drivers/gpu/drm/i915/intel_panel.c            |  10 +-
 drivers/gpu/drm/i915/intel_pipe_crc.c         |   2 +-
 drivers/gpu/drm/i915/intel_pm.c               | 100 ++++-----
 drivers/gpu/drm/i915/intel_psr.c              |   6 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c       |  34 +--
 drivers/gpu/drm/i915/intel_sdvo.c             |  14 +-
 drivers/gpu/drm/i915/intel_sprite.c           |  30 +--
 drivers/gpu/drm/i915/intel_tv.c               |   2 +-
 drivers/gpu/drm/i915/intel_uncore.c           |  20 +-
 .../drm/i915/selftests/i915_gem_coherency.c   |   4 +-
 .../gpu/drm/i915/selftests/i915_gem_context.c |   2 +-
 .../gpu/drm/i915/selftests/i915_gem_object.c  |  12 +-
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |   8 +-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |   2 +-
 51 files changed, 457 insertions(+), 457 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2bdce9fea671..cc9223042a6d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -709,7 +709,7 @@  static int i915_interrupt_info(struct seq_file *m, void *data)
 			   I915_READ(GEN8_PCU_IIR));
 		seq_printf(m, "PCU interrupt enable:\t%08x\n",
 			   I915_READ(GEN8_PCU_IER));
-	} else if (INTEL_GEN(dev_priv) >= 8) {
+	} else if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
 			   I915_READ(GEN8_MASTER_IRQ));
 
@@ -846,7 +846,7 @@  static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
 			   I915_READ(GTIMR));
 	}
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		for_each_engine(engine, dev_priv, id) {
 			seq_printf(m,
 				   "Graphics Interrupt mask (%s):	%08x\n",
@@ -1057,7 +1057,7 @@  static int i915_frequency_info(struct seq_file *m, void *unused)
 			   "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(dev_priv, rps->efficient_freq));
 		mutex_unlock(&dev_priv->pcu_lock);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		u32 rp_state_limits;
 		u32 gt_perf_status;
 		u32 rp_state_cap;
@@ -1081,7 +1081,7 @@  static int i915_frequency_info(struct seq_file *m, void *unused)
 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 		reqf = I915_READ(GEN6_RPNSWREQ);
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			reqf >>= 23;
 		else {
 			reqf &= ~GEN6_TURBO_DISABLE;
@@ -1134,7 +1134,7 @@  static int i915_frequency_info(struct seq_file *m, void *unused)
 			   rps->pm_intrmsk_mbz);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+			   (gt_perf_status & (IS_GEN(dev_priv, 9, GEN_FOREVER) ? 0x1ff00 : 0xff00)) >> 8);
 		seq_printf(m, "Render p-state VID: %d\n",
 			   gt_perf_status & 0xff);
 		seq_printf(m, "Render p-state limit: %d\n",
@@ -1219,13 +1219,13 @@  static void i915_instdone_info(struct drm_i915_private *dev_priv,
 	seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
 		   instdone->instdone);
 
-	if (INTEL_GEN(dev_priv) <= 3)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		return;
 
 	seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
 		   instdone->slice_common);
 
-	if (INTEL_GEN(dev_priv) <= 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6))
 		return;
 
 	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
@@ -1479,7 +1479,7 @@  static int gen6_drpc_info(struct seq_file *m)
 	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
 	rcctl1 = I915_READ(GEN6_RC_CONTROL);
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
 		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
 	}
@@ -1492,7 +1492,7 @@  static int gen6_drpc_info(struct seq_file *m)
 		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
 	seq_printf(m, "RC6 Enabled: %s\n",
 		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		seq_printf(m, "Render Well Gating Enabled: %s\n",
 			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
 		seq_printf(m, "Media Well Gating Enabled: %s\n",
@@ -1526,7 +1526,7 @@  static int gen6_drpc_info(struct seq_file *m)
 
 	seq_printf(m, "Core Power Down: %s\n",
 		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		seq_printf(m, "Render Power Well: %s\n",
 			(gen9_powergate_status &
 			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
@@ -1560,7 +1560,7 @@  static int i915_drpc_info(struct seq_file *m, void *unused)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		err = vlv_drpc_info(m);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		err = gen6_drpc_info(m);
 	else
 		err = ironlake_drpc_info(m);
@@ -1607,11 +1607,11 @@  static int i915_fbc_status(struct seq_file *m, void *unused)
 	if (intel_fbc_is_active(dev_priv)) {
 		u32 mask;
 
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
-		else if (INTEL_GEN(dev_priv) >= 7)
+		else if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
-		else if (INTEL_GEN(dev_priv) >= 5)
+		else if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
 		else if (IS_G4X(dev_priv))
 			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
@@ -1632,7 +1632,7 @@  static int i915_fbc_false_color_get(void *data, u64 *val)
 {
 	struct drm_i915_private *dev_priv = data;
 
-	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6) || !HAS_FBC(dev_priv))
 		return -ENODEV;
 
 	*val = dev_priv->fbc.false_color;
@@ -1645,7 +1645,7 @@  static int i915_fbc_false_color_set(void *data, u64 val)
 	struct drm_i915_private *dev_priv = data;
 	u32 reg;
 
-	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6) || !HAS_FBC(dev_priv))
 		return -ENODEV;
 
 	mutex_lock(&dev_priv->fbc.lock);
@@ -1677,7 +1677,7 @@  static int i915_ips_status(struct seq_file *m, void *unused)
 	seq_printf(m, "Enabled by kernel parameter: %s\n",
 		   yesno(i915_modparams.enable_ips));
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		seq_puts(m, "Currently: unknown\n");
 	} else {
 		if (I915_READ(IPS_CTL) & IPS_ENABLE)
@@ -1699,7 +1699,7 @@  static int i915_sr_status(struct seq_file *m, void *unused)
 	intel_runtime_pm_get(dev_priv);
 	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		/* no global SR status; inspect per-plane WM */;
 	else if (HAS_PCH_SPLIT(dev_priv))
 		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
@@ -1979,7 +1979,7 @@  static int i915_swizzle_info(struct seq_file *m, void *data)
 			   I915_READ16(C0DRB3));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
 			   I915_READ16(C1DRB3));
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   I915_READ(MAD_DIMM_C0));
 		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
@@ -1988,7 +1988,7 @@  static int i915_swizzle_info(struct seq_file *m, void *data)
 			   I915_READ(MAD_DIMM_C2));
 		seq_printf(m, "TILECTL = 0x%08x\n",
 			   I915_READ(TILECTL));
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
 				   I915_READ(GAMTARBMODE));
 		else
@@ -2096,9 +2096,9 @@  static int i915_ppgtt_info(struct seq_file *m, void *data)
 
 	intel_runtime_pm_get(dev_priv);
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		gen8_ppgtt_info(m, dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_ppgtt_info(m, dev_priv);
 
 	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
@@ -2192,7 +2192,7 @@  static int i915_rps_boost_info(struct seq_file *m, void *data)
 		   atomic_read(&rps->boosts));
 	mutex_unlock(&dev->filelist_mutex);
 
-	if (INTEL_GEN(dev_priv) >= 6 &&
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER) &&
 	    rps->enabled &&
 	    dev_priv->gt.active_requests) {
 		u32 rpup, rpupei;
@@ -2223,7 +2223,7 @@  static int i915_rps_boost_info(struct seq_file *m, void *data)
 static int i915_llc(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	const bool edram = INTEL_GEN(dev_priv) > 8;
+	const bool edram = IS_GEN(dev_priv, 9, GEN_FOREVER);
 
 	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
 	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
@@ -2678,7 +2678,7 @@  static int i915_energy_uJ(struct seq_file *m, void *data)
 	unsigned long long power;
 	u32 units;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return -ENODEV;
 
 	intel_runtime_pm_get(dev_priv);
@@ -3293,7 +3293,7 @@  static int i915_ddb_info(struct seq_file *m, void *unused)
 	enum pipe pipe;
 	int plane;
 
-	if (INTEL_GEN(dev_priv) < 9)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8))
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
@@ -3692,7 +3692,7 @@  static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
 		 * - WM1+ latency values in 0.5us units
 		 * - latencies are in us on gen9/vlv/chv
 		 */
-		if (INTEL_GEN(dev_priv) >= 9 ||
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER) ||
 		    IS_VALLEYVIEW(dev_priv) ||
 		    IS_CHERRYVIEW(dev_priv) ||
 		    IS_G4X(dev_priv))
@@ -3712,7 +3712,7 @@  static int pri_wm_latency_show(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = m->private;
 	const uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.pri_latency;
@@ -3727,7 +3727,7 @@  static int spr_wm_latency_show(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = m->private;
 	const uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.spr_latency;
@@ -3742,7 +3742,7 @@  static int cur_wm_latency_show(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = m->private;
 	const uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.cur_latency;
@@ -3756,7 +3756,7 @@  static int pri_wm_latency_open(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *dev_priv = inode->i_private;
 
-	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv))
 		return -ENODEV;
 
 	return single_open(file, pri_wm_latency_show, dev_priv);
@@ -3835,7 +3835,7 @@  static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
 	struct drm_i915_private *dev_priv = m->private;
 	uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.pri_latency;
@@ -3850,7 +3850,7 @@  static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
 	struct drm_i915_private *dev_priv = m->private;
 	uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.spr_latency;
@@ -3865,7 +3865,7 @@  static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	struct drm_i915_private *dev_priv = m->private;
 	uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.cur_latency;
@@ -4103,7 +4103,7 @@  i915_max_freq_get(void *data, u64 *val)
 {
 	struct drm_i915_private *dev_priv = data;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return -ENODEV;
 
 	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
@@ -4118,7 +4118,7 @@  i915_max_freq_set(void *data, u64 val)
 	u32 hw_max, hw_min;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return -ENODEV;
 
 	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
@@ -4159,7 +4159,7 @@  i915_min_freq_get(void *data, u64 *val)
 {
 	struct drm_i915_private *dev_priv = data;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return -ENODEV;
 
 	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
@@ -4174,7 +4174,7 @@  i915_min_freq_set(void *data, u64 val)
 	u32 hw_max, hw_min;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return -ENODEV;
 
 	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
@@ -4472,7 +4472,7 @@  static int i915_sseu_status(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct sseu_dev_info sseu;
 
-	if (INTEL_GEN(dev_priv) < 8)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 7))
 		return -ENODEV;
 
 	seq_puts(m, "SSEU Device Info\n");
@@ -4489,7 +4489,7 @@  static int i915_sseu_status(struct seq_file *m, void *unused)
 		broadwell_sseu_device_status(dev_priv, &sseu);
 	} else if (IS_GEN9(dev_priv)) {
 		gen9_sseu_device_status(dev_priv, &sseu);
-	} else if (INTEL_GEN(dev_priv) >= 10) {
+	} else if (IS_GEN(dev_priv, 10, GEN_FOREVER)) {
 		gen10_sseu_device_status(dev_priv, &sseu);
 	}
 
@@ -4504,7 +4504,7 @@  static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
 
-	if (INTEL_GEN(i915) < 6)
+	if (IS_GEN(i915, GEN_FOREVER, 5))
 		return 0;
 
 	intel_runtime_pm_get(i915);
@@ -4517,7 +4517,7 @@  static int i915_forcewake_release(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
 
-	if (INTEL_GEN(i915) < 6)
+	if (IS_GEN(i915, GEN_FOREVER, 5))
 		return 0;
 
 	intel_uncore_forcewake_user_put(i915);
@@ -4615,7 +4615,7 @@  static int i915_drrs_ctl_set(void *data, u64 val)
 	struct intel_encoder *encoder;
 	struct intel_dp *intel_dp;
 
-	if (INTEL_GEN(dev_priv) < 7)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6))
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cd57f946cf45..f50523f56071 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -453,12 +453,12 @@  static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 static int
 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 {
-	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int reg = IS_GEN(dev_priv, 4, GEN_FOREVER) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp_lo, temp_hi = 0;
 	u64 mchbar_addr;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -485,7 +485,7 @@  intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 		return ret;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 				       upper_32_bits(dev_priv->mch_res.start));
 
@@ -498,7 +498,7 @@  intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 static void
 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 {
-	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int mchbar_reg = IS_GEN(dev_priv, 4, GEN_FOREVER) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 	bool enabled;
 
@@ -537,7 +537,7 @@  intel_setup_mchbar(struct drm_i915_private *dev_priv)
 static void
 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 {
-	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int mchbar_reg = IS_GEN(dev_priv, 4, GEN_FOREVER) ? MCHBAR_I965 : MCHBAR_I915;
 
 	if (dev_priv->mchbar_need_disable) {
 		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
@@ -978,7 +978,7 @@  static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 	 * the register BAR remains the same size for all the earlier
 	 * generations up to Ironlake.
 	 */
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		mmio_size = 512 * 1024;
 	else
 		mmio_size = 2 * 1024 * 1024;
@@ -1176,7 +1176,7 @@  static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	 * properly dead afterwards. So we'll just disable them for all
 	 * pre-gen5 chipsets.
 	 */
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		if (pci_enable_msi(pdev) < 0)
 			DRM_DEBUG_DRIVER("can't enable MSI");
 	}
@@ -1667,7 +1667,7 @@  static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 	 * Fujitsu FSC S7110
 	 * Acer Aspire 1830T
 	 */
-	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
+	if (!(hibernation && IS_GEN(dev_priv, GEN_FOREVER, 5)))
 		pci_set_power_state(pdev, PCI_D3hot);
 
 	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e65e0bc3d09..6f56f3a42cd1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2833,7 +2833,7 @@  intel_info(const struct drm_i915_private *dev_priv)
  * interrupts.
  */
 #define HAS_AUX_IRQ(dev_priv)   true
-#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
+#define HAS_GMBUS_IRQ(dev_priv) (IS_GEN(dev_priv, 4, GEN_FOREVER))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
@@ -2844,7 +2844,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
 #define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
 
-#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
+#define HAS_FW_BLC(dev_priv) 	(IS_GEN(dev_priv, 3, GEN_FOREVER))
 #define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
 #define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
 
@@ -2929,7 +2929,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
 
-#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
+#define HAS_LSPCON(dev_priv) (IS_GEN(dev_priv, 9, GEN_FOREVER))
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
@@ -2952,7 +2952,7 @@  static inline bool intel_vtd_active(void)
 
 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
+	return IS_GEN(dev_priv, 6, GEN_FOREVER) && intel_vtd_active();
 }
 
 static inline bool
@@ -3539,7 +3539,7 @@  void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {
 	wmb();
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		intel_gtt_chipset_flush();
 }
 
@@ -3974,7 +3974,7 @@  static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
 {
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return VLV_VGACNTRL;
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		return CPU_VGACNTRL;
 	else
 		return VGACNTRL;
@@ -4142,7 +4142,7 @@  int remap_io_mapping(struct vm_area_struct *vma,
 
 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) >= 10)
+	if (IS_GEN(i915, 10, GEN_FOREVER))
 		return CNL_HWS_CSB_WRITE_INDEX;
 	else
 		return I915_HWS_CSB_WRITE_INDEX;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fc68b35854df..46fe9ba6a5e8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -386,7 +386,7 @@  i915_gem_object_wait_fence(struct dma_fence *fence,
 	 * each client to waitboost once in a busy period.
 	 */
 	if (rps_client && !i915_gem_request_started(rq)) {
-		if (INTEL_GEN(rq->i915) >= 6)
+		if (IS_GEN(rq->i915, 6, GEN_FOREVER))
 			gen6_rps_boost(rq, rps_client);
 	}
 
@@ -3148,7 +3148,7 @@  void i915_gem_reset(struct drm_i915_private *dev_priv)
 	if (dev_priv->gt.awake) {
 		intel_sanitize_gt_powersave(dev_priv);
 		intel_enable_gt_powersave(dev_priv);
-		if (INTEL_GEN(dev_priv) >= 6)
+		if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 			gen6_rps_busy(dev_priv);
 	}
 }
@@ -3480,7 +3480,7 @@  i915_gem_idle_work_handler(struct work_struct *work)
 	GEM_BUG_ON(epoch == I915_EPOCH_INVALID);
 	rearm_hangcheck = false;
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_rps_idle(dev_priv);
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
@@ -4888,7 +4888,7 @@  void i915_gem_sanitize(struct drm_i915_private *i915)
 	 * it may impact the display and we are uncertain about the stability
 	 * of the reset, so this could be applied to even earlier gen.
 	 */
-	if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915))
+	if (IS_GEN(i915, 5, GEN_FOREVER) && intel_has_gpu_reset(i915))
 		WARN_ON(intel_gpu_reset(i915, ALL_ENGINES));
 }
 
@@ -5014,7 +5014,7 @@  void i915_gem_resume(struct drm_i915_private *i915)
 
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 5 ||
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) ||
 	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 		return;
 
@@ -5088,7 +5088,7 @@  int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	/* Double layer security blanket, see i915_gem_init() */
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
+	if (HAS_EDRAM(dev_priv) && IS_GEN(dev_priv, GEN_FOREVER, 8))
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
 	if (IS_HASWELL(dev_priv))
@@ -5100,7 +5100,7 @@  int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 			u32 temp = I915_READ(GEN7_MSG_CTL);
 			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
 			I915_WRITE(GEN7_MSG_CTL, temp);
-		} else if (INTEL_GEN(dev_priv) >= 7) {
+		} else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
 			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
 			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
@@ -5424,10 +5424,10 @@  i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
 {
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER) && !IS_VALLEYVIEW(dev_priv) &&
 	    !IS_CHERRYVIEW(dev_priv))
 		dev_priv->num_fence_regs = 32;
-	else if (INTEL_GEN(dev_priv) >= 4 ||
+	else if (IS_GEN(dev_priv, 4, GEN_FOREVER) ||
 		 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 		 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
 		dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index d6a1f2ce1fcd..22b8ba9c94a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2522,7 +2522,7 @@  i915_gem_execbuffer(struct drm_device *dev, void *data,
 		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
 		exec2_list[i].alignment = exec_list[i].alignment;
 		exec2_list[i].offset = exec_list[i].offset;
-		if (INTEL_GEN(to_i915(dev)) < 4)
+		if (IS_GEN(to_i915(dev), GEN_FOREVER, 3))
 			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
 		else
 			exec2_list[i].flags = 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index b8338d75c6f3..30a1d0d7e5e3 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -557,7 +557,7 @@  i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER) || IS_VALLEYVIEW(dev_priv)) {
 		/*
 		 * On BDW+, swizzling is not used. We leave the CPU memory
 		 * controller in charge of optimizing memory accesses without
@@ -567,7 +567,7 @@  i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
 		 */
 		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		if (dev_priv->preserve_bios_swizzle) {
 			if (I915_READ(DISP_ARB_CTL) &
 			    DISP_TILE_SURFACE_SWIZZLING) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0c0f1affddad..9a596af3e827 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -154,7 +154,7 @@  int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 	 * execlists, the sole mechanism available to submit work.
 	 */
-	if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
+	if (enable_ppgtt == 0 && IS_GEN(dev_priv, GEN_FOREVER, 8))
 		return 0;
 
 	if (enable_ppgtt == 1)
@@ -2109,7 +2109,7 @@  static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
 	ppgtt->base.i915 = dev_priv;
 	ppgtt->base.dma = &dev_priv->drm.pdev->dev;
 
-	if (INTEL_GEN(dev_priv) < 8)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 7))
 		return gen6_ppgtt_init(ppgtt);
 	else
 		return gen8_ppgtt_init(ppgtt);
@@ -2170,7 +2170,7 @@  static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * driver.
 	 */
 	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
-	    INTEL_GEN(dev_priv) <= 10)
+	    IS_GEN(dev_priv, GEN_FOREVER, 10))
 		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
 			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
 			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
@@ -2193,7 +2193,7 @@  int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 		gen6_ppgtt_enable(dev_priv);
 	else if (IS_GEN7(dev_priv))
 		gen7_ppgtt_enable(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 8)
+	else if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		gen8_ppgtt_enable(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
@@ -2338,9 +2338,9 @@  static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
 {
 	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		gen8_check_and_clear_faults(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_check_and_clear_faults(dev_priv);
 	else
 		return;
@@ -2353,7 +2353,7 @@  void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 	/* Don't bother messing with faults pre GEN6 as we have little
 	 * documentation supporting that it's a good idea.
 	 */
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return;
 
 	i915_check_and_clear_faults(dev_priv);
@@ -2999,7 +2999,7 @@  static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
 	 */
-	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN9_LP(dev_priv) || IS_GEN(dev_priv, 10, GEN_FOREVER))
 		ggtt->gsm = ioremap_nocache(phys_addr, size);
 	else
 		ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3294,7 +3294,7 @@  static void setup_private_pat(struct drm_i915_private *dev_priv)
 
 	ppat->i915 = dev_priv;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		cnl_setup_private_ppat(ppat);
 	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 		chv_setup_private_ppat(ppat);
@@ -3334,7 +3334,7 @@  static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		size = chv_get_total_gtt_size(snb_gmch_ctl);
@@ -3418,7 +3418,7 @@  static int gen6_gmch_probe(struct i915_ggtt *ggtt)
 		ggtt->base.pte_encode = hsw_pte_encode;
 	else if (IS_VALLEYVIEW(dev_priv))
 		ggtt->base.pte_encode = byt_pte_encode;
-	else if (INTEL_GEN(dev_priv) >= 7)
+	else if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		ggtt->base.pte_encode = ivb_pte_encode;
 	else
 		ggtt->base.pte_encode = snb_pte_encode;
@@ -3481,9 +3481,9 @@  int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
 	ggtt->base.i915 = dev_priv;
 	ggtt->base.dma = &dev_priv->drm.pdev->dev;
 
-	if (INTEL_GEN(dev_priv) <= 5)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		ret = i915_gmch_probe(ggtt);
-	else if (INTEL_GEN(dev_priv) < 8)
+	else if (IS_GEN(dev_priv, GEN_FOREVER, 7))
 		ret = gen6_gmch_probe(ggtt);
 	else
 		ret = gen8_gmch_probe(ggtt);
@@ -3574,7 +3574,7 @@  int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 
 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5) && !intel_enable_gtt())
 		return -EIO;
 
 	return 0;
@@ -3631,7 +3631,7 @@  void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 
 	ggtt->base.closed = false;
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		struct intel_ppat *ppat = &dev_priv->ppat;
 
 		bitmap_set(ppat->dirty, 0, ppat->max_entries);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 8bc7c50b8418..977f023b79bd 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -279,7 +279,7 @@  static void mark_busy(struct drm_i915_private *i915)
 
 	intel_enable_gt_powersave(i915);
 	i915_update_gfx_val(i915);
-	if (INTEL_GEN(i915) >= 6)
+	if (IS_GEN(i915, 6, GEN_FOREVER))
 		gen6_rps_busy(i915);
 	i915_pmu_gt_unparked(i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f18da9e2be8e..0afd50cf71de 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -91,7 +91,7 @@  static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
 	 */
 
 	/* Make sure we don't clobber the GTT if it's within stolen memory */
-	if (INTEL_GEN(dev_priv) <= 4 &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) &&
 	    !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) {
 		struct resource stolen[2] = {*dsm, *dsm};
 		struct resource ggtt_res;
@@ -336,7 +336,7 @@  int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 		return 0;
 	}
 
-	if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
+	if (intel_vtd_active() && IS_GEN(dev_priv, GEN_FOREVER, 7)) {
 		DRM_INFO("DMAR active, disabling use of stolen memory\n");
 		return 0;
 	}
@@ -412,7 +412,7 @@  int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 
 	stolen_usable_start = 0;
 	/* WaSkipStolenMemoryFirstPage:bdw+ */
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		stolen_usable_start = 4096;
 
 	dev_priv->stolen_usable_size =
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index d9dc9df523b5..405b8b223c24 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -80,7 +80,7 @@  u32 i915_gem_fence_size(struct drm_i915_private *i915,
 
 	GEM_BUG_ON(!stride);
 
-	if (INTEL_GEN(i915) >= 4) {
+	if (IS_GEN(i915, 4, GEN_FOREVER)) {
 		stride *= i915_gem_tile_height(tiling);
 		GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
 		return roundup(size, stride);
@@ -120,7 +120,7 @@  u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
 	if (tiling == I915_TILING_NONE)
 		return I915_GTT_MIN_ALIGNMENT;
 
-	if (INTEL_GEN(i915) >= 4)
+	if (IS_GEN(i915, 4, GEN_FOREVER))
 		return I965_FENCE_PAGE;
 
 	/*
@@ -148,10 +148,10 @@  i915_tiling_ok(struct drm_i915_gem_object *obj,
 	/* check maximum stride & object size */
 	/* i965+ stores the end address of the gtt mapping in the fence
 	 * reg, so dont bother to check the size */
-	if (INTEL_GEN(i915) >= 7) {
+	if (IS_GEN(i915, 7, GEN_FOREVER)) {
 		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
 			return false;
-	} else if (INTEL_GEN(i915) >= 4) {
+	} else if (IS_GEN(i915, 4, GEN_FOREVER)) {
 		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 			return false;
 	} else {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 161d9103a65e..01c02931ad90 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -376,13 +376,13 @@  static void error_print_instdone(struct drm_i915_error_state_buf *m,
 	err_printf(m, "  INSTDONE: 0x%08x\n",
 		   ee->instdone.instdone);
 
-	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
+	if (ee->engine_id != RCS || IS_GEN(m->i915, GEN_FOREVER, 3))
 		return;
 
 	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 		   ee->instdone.slice_common);
 
-	if (INTEL_GEN(m->i915) <= 6)
+	if (IS_GEN(m->i915, GEN_FOREVER, 6))
 		return;
 
 	for_each_instdone_slice_subslice(m->i915, slice, subslice)
@@ -455,7 +455,7 @@  static void error_print_engine(struct drm_i915_error_state_buf *m,
 			   upper_32_bits(start), lower_32_bits(start),
 			   upper_32_bits(end), lower_32_bits(end));
 	}
-	if (INTEL_GEN(m->i915) >= 4) {
+	if (IS_GEN(m->i915, 4, GEN_FOREVER)) {
 		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
@@ -464,7 +464,7 @@  static void error_print_engine(struct drm_i915_error_state_buf *m,
 	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 		   lower_32_bits(ee->faddr));
-	if (INTEL_GEN(m->i915) >= 6) {
+	if (IS_GEN(m->i915, 6, GEN_FOREVER)) {
 		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 		err_printf(m, "  SYNC_0: 0x%08x\n",
@@ -478,7 +478,7 @@  static void error_print_engine(struct drm_i915_error_state_buf *m,
 	if (USES_PPGTT(m->i915)) {
 		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 
-		if (INTEL_GEN(m->i915) >= 8) {
+		if (IS_GEN(m->i915, 8, GEN_FOREVER)) {
 			int i;
 			for (i = 0; i < 4; i++)
 				err_printf(m, "  PDP%d: 0x%016llx\n",
@@ -693,10 +693,10 @@  int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	for (i = 0; i < error->nfence; i++)
 		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		err_printf(m, "ERROR: 0x%08x\n", error->error);
 
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 				   error->fault_data1, error->fault_data0);
 
@@ -1089,10 +1089,10 @@  static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
 {
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
 	} else {
@@ -1194,9 +1194,9 @@  static void error_record_engine_registers(struct i915_gpu_state *error,
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
-		if (INTEL_GEN(dev_priv) >= 8) {
+		if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
 		} else {
 			gen6_record_semaphore_state(engine, ee);
@@ -1204,13 +1204,13 @@  static void error_record_engine_registers(struct i915_gpu_state *error,
 		}
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
 		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
 		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
 		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
 		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
-		if (INTEL_GEN(dev_priv) >= 8) {
+		if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
 			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
 		}
@@ -1232,7 +1232,7 @@  static void error_record_engine_registers(struct i915_gpu_state *error,
 	ee->head = I915_READ_HEAD(engine);
 	ee->tail = I915_READ_TAIL(engine);
 	ee->ctl = I915_READ_CTL(engine);
-	if (INTEL_GEN(dev_priv) > 2)
+	if (IS_GEN(dev_priv, 3, GEN_FOREVER))
 		ee->mode = I915_READ_MODE(engine);
 
 	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
@@ -1282,7 +1282,7 @@  static void error_record_engine_registers(struct i915_gpu_state *error,
 		else if (IS_GEN7(dev_priv))
 			ee->vm_info.pp_dir_base =
 				I915_READ(RING_PP_DIR_BASE(engine));
-		else if (INTEL_GEN(dev_priv) >= 8)
+		else if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 			for (i = 0; i < 4; i++) {
 				ee->vm_info.pdp[i] =
 					I915_READ(GEN8_RING_PDP_UDW(engine, i));
@@ -1649,7 +1649,7 @@  static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	if (IS_GEN7(dev_priv))
 		error->err_int = I915_READ(GEN7_ERR_INT);
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
 		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
 	}
@@ -1661,16 +1661,16 @@  static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	}
 
 	/* 2: Registers which belong to multiple generations */
-	if (INTEL_GEN(dev_priv) >= 7)
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		error->derrmr = I915_READ(DERRMR);
 		error->error = I915_READ(ERROR_GEN6);
 		error->done_reg = I915_READ(DONE_REG);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		error->ccid = I915_READ(CCID);
 
 	/* 3: Feature specific registers */
@@ -1680,7 +1680,7 @@  static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	}
 
 	/* 4: Everything else */
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		error->ier = I915_READ(GEN8_DE_MISC_IER);
 		for (i = 0; i < 4; i++)
 			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..8e33f6399aad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -308,17 +308,17 @@  void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 
 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
+	return IS_GEN(dev_priv, 8, GEN_FOREVER) ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
 
 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
+	return IS_GEN(dev_priv, 8, GEN_FOREVER) ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 }
 
 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
+	return IS_GEN(dev_priv, 8, GEN_FOREVER) ? GEN8_GT_IER(2) : GEN6_PMIER;
 }
 
 /**
@@ -585,7 +585,7 @@  u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		goto out;
 
 	/*
@@ -676,7 +676,7 @@  static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		i915_enable_pipestat(dev_priv, PIPE_A,
 				     PIPE_LEGACY_BLC_EVENT_STATUS);
 
@@ -947,7 +947,7 @@  static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 	if (stime)
 		*stime = ktime_get();
 
-	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		/* No obvious pixelcount register. Only query vertical
 		 * scanout position from Display scan line register.
 		 */
@@ -1007,7 +1007,7 @@  static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 	else
 		position += vtotal - vbl_end;
 
-	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		*vpos = position;
 		*hpos = 0;
 	} else {
@@ -1652,7 +1652,7 @@  static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 		 * don't trust that one either.
 		 */
 		if (pipe_crc->skipped == 0 ||
-		    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+		    (IS_GEN(dev_priv, 8, GEN_FOREVER) && pipe_crc->skipped == 1)) {
 			pipe_crc->skipped++;
 			spin_unlock(&pipe_crc->lock);
 			return;
@@ -1702,12 +1702,12 @@  static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 {
 	uint32_t res1, res2;
 
-	if (INTEL_GEN(dev_priv) >= 3)
+	if (IS_GEN(dev_priv, 3, GEN_FOREVER))
 		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
 	else
 		res1 = 0;
 
-	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv))
 		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
 	else
 		res2 = 0;
@@ -1736,7 +1736,7 @@  static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 		spin_unlock(&dev_priv->irq_lock);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		return;
 
 	if (HAS_VEBOX(dev_priv)) {
@@ -2482,7 +2482,7 @@  static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	if (gt_iir) {
 		I915_WRITE(GTIIR, gt_iir);
 		ret = IRQ_HANDLED;
-		if (INTEL_GEN(dev_priv) >= 6)
+		if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 			snb_gt_irq_handler(dev_priv, gt_iir);
 		else
 			ilk_gt_irq_handler(dev_priv, gt_iir);
@@ -2492,13 +2492,13 @@  static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	if (de_iir) {
 		I915_WRITE(DEIIR, de_iir);
 		ret = IRQ_HANDLED;
-		if (INTEL_GEN(dev_priv) >= 7)
+		if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 			ivb_display_irq_handler(dev_priv, de_iir);
 		else
 			ilk_display_irq_handler(dev_priv, de_iir);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		u32 pm_iir = I915_READ(GEN6_PMIIR);
 		if (pm_iir) {
 			I915_WRITE(GEN6_PMIIR, pm_iir);
@@ -2567,7 +2567,7 @@  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			ret = IRQ_HANDLED;
 
 			tmp_mask = GEN8_AUX_CHANNEL_A;
-			if (INTEL_GEN(dev_priv) >= 9)
+			if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 				tmp_mask |= GEN9_AUX_CHANNEL_B |
 					    GEN9_AUX_CHANNEL_C |
 					    GEN9_AUX_CHANNEL_D;
@@ -2633,7 +2633,7 @@  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
 
 		fault_errors = iir;
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
 		else
 			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -2802,7 +2802,7 @@  static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
 	if (!IS_GEN2(dev_priv))
 		I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		I915_WRITE(IPEIR, I915_READ(IPEIR));
 	else
 		I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
@@ -2944,7 +2944,7 @@  static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	unsigned long irqflags;
-	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
+	uint32_t bit = IS_GEN(dev_priv, 7, GEN_FOREVER) ?
 		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2994,7 +2994,7 @@  static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	unsigned long irqflags;
-	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
+	uint32_t bit = IS_GEN(dev_priv, 7, GEN_FOREVER) ?
 		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -3046,7 +3046,7 @@  static void ibx_irq_pre_postinstall(struct drm_device *dev)
 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
 {
 	GEN3_IRQ_RESET(GT);
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		GEN3_IRQ_RESET(GEN6_PM);
 }
 
@@ -3330,12 +3330,12 @@  static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
 		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
 
 		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
-	} else if (INTEL_GEN(dev_priv) >= 7) {
+	} else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
 		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
 
@@ -3448,7 +3448,7 @@  static void gen5_gt_irq_postinstall(struct drm_device *dev)
 
 	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		/*
 		 * RPS interrupts will get enabled/disabled on demand when RPS
 		 * itself is enabled/disabled.
@@ -3468,7 +3468,7 @@  static int ironlake_irq_postinstall(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	u32 display_mask, extra_mask;
 
-	if (INTEL_GEN(dev_priv) >= 7) {
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
 				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
 		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
@@ -3596,7 +3596,7 @@  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 de_misc_masked = GEN8_DE_MISC_GSE;
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
 		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
 				  GEN9_AUX_CHANNEL_D;
@@ -4048,16 +4048,16 @@  void intel_irq_init(struct drm_i915_private *dev_priv)
 	 *
 	 * TODO: verify if this can be reproduced on VLV,CHV.
 	 */
-	if (INTEL_GEN(dev_priv) <= 7)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 7))
 		rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
 	if (IS_GEN2(dev_priv)) {
 		/* Gen2 doesn't have a hardware frame counter */
 		dev->max_vblank_count = 0;
-	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
 	} else {
@@ -4104,7 +4104,7 @@  void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->enable_vblank = i965_enable_vblank;
 		dev->driver->disable_vblank = i965_disable_vblank;
 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
-	} else if (INTEL_GEN(dev_priv) >= 8) {
+	} else if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
 		dev->driver->irq_postinstall = gen8_irq_postinstall;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f0cfdece14ae..084e5331ab70 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3253,7 +3253,7 @@  int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
 		goto reg_err;
 	}
 
-	if (INTEL_GEN(dev_priv) < 8) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 7)) {
 		if (args->n_flex_regs != 0) {
 			err = -EINVAL;
 			goto reg_err;
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 964467b03e4d..1eec8ef34769 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -319,7 +319,7 @@  engine_event_status(struct intel_engine_cs *engine,
 	case I915_SAMPLE_WAIT:
 		break;
 	case I915_SAMPLE_SEMA:
-		if (INTEL_GEN(engine->i915) < 6)
+		if (IS_GEN(engine->i915, GEN_FOREVER, 5))
 			return -ENODEV;
 		break;
 	default:
@@ -339,7 +339,7 @@  config_status(struct drm_i915_private *i915, u64 config)
 			return -ENODEV;
 		/* Fall-through. */
 	case I915_PMU_REQUESTED_FREQUENCY:
-		if (INTEL_GEN(i915) < 6)
+		if (IS_GEN(i915, GEN_FOREVER, 5))
 			return -ENODEV;
 		break;
 	case I915_PMU_INTERRUPTS:
@@ -1018,7 +1018,7 @@  void i915_pmu_register(struct drm_i915_private *i915)
 {
 	int ret;
 
-	if (INTEL_GEN(i915) <= 2) {
+	if (IS_GEN(i915, GEN_FOREVER, 2)) {
 		DRM_INFO("PMU not supported for this GPU.");
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b560823..0365ea79a10f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3792,7 +3792,7 @@  enum i915_power_well_id {
 #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
 #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
-#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
+#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN(dev_priv, 9, GEN_FOREVER) ? \
 				(IS_GEN9_LP(dev_priv) ? \
 				INTERVAL_0_833_US(us) : \
 				INTERVAL_1_33_US(us)) : \
@@ -3801,7 +3801,7 @@  enum i915_power_well_id {
 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
-#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
+#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN(dev_priv, 9, GEN_FOREVER) ? \
                            (IS_GEN9_LP(dev_priv) ? \
                            INTERVAL_0_833_TO_US(interval) : \
                            INTERVAL_1_33_TO_US(interval)) : \
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8f3aa4dc0c98..5725fa72744e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,25 +32,25 @@ 
 static void i915_save_display(struct drm_i915_private *dev_priv)
 {
 	/* Display arbitration control */
-	if (INTEL_GEN(dev_priv) <= 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
 	/* save FBC interval */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
+	if (HAS_FBC(dev_priv) && IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv))
 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 }
 
 static void i915_restore_display(struct drm_i915_private *dev_priv)
 {
 	/* Display arbitration */
-	if (INTEL_GEN(dev_priv) <= 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
 
 	/* only restore FBC info on the platform that supports FBC*/
 	intel_fbc_global_disable(dev_priv);
 
 	/* restore FBC interval */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
+	if (HAS_FBC(dev_priv) && IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv))
 		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
 	i915_redisable_vga(dev_priv);
@@ -70,7 +70,7 @@  int i915_save_state(struct drm_i915_private *dev_priv)
 				     &dev_priv->regfile.saveGCDGMBUS);
 
 	/* Cache mode state */
-	if (INTEL_GEN(dev_priv) < 7)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6))
 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
 	/* Memory Arbitration state */
@@ -114,7 +114,7 @@  int i915_restore_state(struct drm_i915_private *dev_priv)
 	i915_restore_display(dev_priv);
 
 	/* Cache mode state */
-	if (INTEL_GEN(dev_priv) < 7)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6))
 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 			   0xffff0000);
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index c74a20b80182..04503cbd38c3 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -611,7 +611,7 @@  void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 	ret = 0;
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
 	if (ret)
 		DRM_ERROR("RPS sysfs setup failed\n");
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 0ee32275994a..268e2a5218e3 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -172,7 +172,7 @@  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	 * Y-tiling is not supported in IF-ID Interlace mode in
 	 * GEN9 and above.
 	 */
-	if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
+	if (state->fb && IS_GEN(dev_priv, 9, GEN_FOREVER) && crtc_state->base.enable &&
 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 		    state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index ff455c724775..ef7bd1375979 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -704,7 +704,7 @@  void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
-	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
+	} else if (IS_HASWELL(dev_priv) || IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index aab6d1538fff..459152d63629 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1895,7 +1895,7 @@  void intel_set_cdclk(struct drm_i915_private *dev_priv,
 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
 				     int pixel_rate)
 {
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		return DIV_ROUND_UP(pixel_rate, 2);
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
@@ -1950,7 +1950,7 @@  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	/* According to BSpec, "The CD clock frequency must be at least twice
 	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
 	 */
-	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
+	if (crtc_state->has_audio && IS_GEN(dev_priv, 9, GEN_FOREVER))
 		min_cdclk = max(2 * 96000, min_cdclk);
 
 	/*
@@ -2220,7 +2220,7 @@  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		return 2 * max_cdclk_freq;
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
@@ -2233,7 +2233,7 @@  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 		return max_cdclk_freq;
 	else if (IS_CHERRYVIEW(dev_priv))
 		return max_cdclk_freq*95/100;
-	else if (INTEL_GEN(dev_priv) < 4)
+	else if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		return 2*max_cdclk_freq*90/100;
 	else
 		return max_cdclk_freq*90/100;
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index aa66e952a95d..81a845520c80 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -222,7 +222,7 @@  static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
 	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 
-	if (INTEL_GEN(dev_priv) > 6) {
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		uint16_t postoff = 0;
 
 		if (intel_crtc_state->limited_color_range)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d1493ced16f8..a2a8c685d28e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -154,7 +154,7 @@  static void intel_crt_set_dpms(struct intel_encoder *encoder,
 	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 	u32 adpa;
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		adpa = ADPA_HOTPLUG_BITS;
 	else
 		adpa = 0;
@@ -799,7 +799,7 @@  intel_crt_detect(struct drm_connector *connector,
 	if (ret > 0) {
 		if (intel_crt_detect_ddc(connector))
 			status = connector_status_connected;
-		else if (INTEL_GEN(dev_priv) < 4)
+		else if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 			status = intel_crt_load_detect(crt,
 				to_intel_crtc(connector->state->crtc)->pipe);
 		else if (i915_modparams.load_detect_test)
@@ -855,7 +855,7 @@  void intel_crt_reset(struct drm_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		u32 adpa;
 
 		adpa = I915_READ(crt->adpa_reg);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8ca376aca8bd..84ae60b8c010 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1458,7 +1458,7 @@  static void intel_ddi_clock_get(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (INTEL_GEN(dev_priv) <= 8)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8))
 		hsw_ddi_clock_get(encoder, pipe_config);
 	else if (IS_GEN9_BC(dev_priv))
 		skl_ddi_clock_get(encoder, pipe_config);
@@ -2152,7 +2152,7 @@  static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		I915_WRITE(DPLL_CTRL2, val);
 
-	} else if (INTEL_GEN(dev_priv) < 9) {
+	} else if (IS_GEN(dev_priv, GEN_FOREVER, 8)) {
 		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
 	}
 
@@ -2170,7 +2170,7 @@  static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	else if (IS_GEN9_BC(dev_priv))
 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
 			   DPLL_CTRL2_DDI_CLK_OFF(port));
-	else if (INTEL_GEN(dev_priv) < 9)
+	else if (IS_GEN(dev_priv, GEN_FOREVER, 8))
 		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 }
 
@@ -2207,7 +2207,7 @@  static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_start_link_train(intel_dp);
-	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+	if (port != PORT_A || IS_GEN(dev_priv, 9, GEN_FOREVER))
 		intel_dp_stop_link_train(intel_dp);
 }
 
@@ -2409,7 +2409,7 @@  static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
 
-	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
+	if (port == PORT_A && IS_GEN(dev_priv, GEN_FOREVER, 8))
 		intel_dp_stop_link_train(intel_dp);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3983d6a44f78..198218d8f224 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -380,7 +380,7 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	u32 f19_2_mhz = 19200;
 	u32 f24_mhz = 24000;
 
-	if (INTEL_GEN(dev_priv) <= 4) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4)) {
 		/* PRMs say:
 		 *
 		 *     "The value in this register increments once every 16
@@ -388,7 +388,7 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *      (“CLKCFG”) MCHBAR register)
 		 */
 		return dev_priv->rawclk_freq / 16;
-	} else if (INTEL_GEN(dev_priv) <= 8) {
+	} else if (IS_GEN(dev_priv, GEN_FOREVER, 8)) {
 		/* PRMs say:
 		 *
 		 *     "The PCU TSC counts 10ns increments; this timestamp
@@ -396,7 +396,7 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *      rolling over every 1.5 hours).
 		 */
 		return f12_5_mhz;
-	} else if (INTEL_GEN(dev_priv) <= 9) {
+	} else if (IS_GEN(dev_priv, GEN_FOREVER, 9)) {
 		u32 ctc_reg = I915_READ(CTC_MODE);
 		u32 freq = 0;
 
@@ -414,7 +414,7 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		}
 
 		return freq;
-	} else if (INTEL_GEN(dev_priv) <= 10) {
+	} else if (IS_GEN(dev_priv, GEN_FOREVER, 10)) {
 		u32 ctc_reg = I915_READ(CTC_MODE);
 		u32 freq = 0;
 		u32 rpm_config_reg = 0;
@@ -480,7 +480,7 @@  void intel_device_info_runtime_init(struct intel_device_info *info)
 		container_of(info, struct drm_i915_private, info);
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER)) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_scalers[pipe] = 2;
 	} else if (IS_GEN9(dev_priv)) {
@@ -507,7 +507,7 @@  void intel_device_info_runtime_init(struct intel_device_info *info)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 2;
-	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+	} else if (IS_GEN(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 1;
 	}
@@ -580,7 +580,7 @@  void intel_device_info_runtime_init(struct intel_device_info *info)
 		broadwell_sseu_info_init(dev_priv);
 	else if (IS_GEN9(dev_priv))
 		gen9_sseu_info_init(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 10)
+	else if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		gen10_sseu_info_init(dev_priv);
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d5207dbfdac..f7a3cefaaaed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1044,7 +1044,7 @@  intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 		i915_reg_t reg = PIPECONF(cpu_transcoder);
 
@@ -1542,7 +1542,7 @@  static void i9xx_enable_pll(struct intel_crtc *crtc,
 	POSTING_READ(reg);
 	udelay(150);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		I915_WRITE(DPLL_MD(crtc->pipe),
 			   crtc_state->dpll_hw_state.dpll_md);
 	} else {
@@ -2029,12 +2029,12 @@  static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
 
 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return 256 * 1024;
 	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
 		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return 128 * 1024;
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		return 4 * 1024;
 	else
 		return 0;
@@ -2053,7 +2053,7 @@  static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case DRM_FORMAT_MOD_LINEAR:
 		return intel_linear_alignment(dev_priv);
 	case I915_FORMAT_MOD_X_TILED:
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -3163,7 +3163,7 @@  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
 
 	switch (fb->format->format) {
@@ -3193,7 +3193,7 @@  static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 		return 0;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4 &&
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER) &&
 	    fb->modifier == I915_FORMAT_MOD_X_TILED)
 		dspcntr |= DISPPLANE_TILED;
 
@@ -3216,7 +3216,7 @@  int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 
 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		offset = intel_compute_tile_offset(&src_x, &src_y,
 						   plane_state, 0);
 	else
@@ -3260,14 +3260,14 @@  static void i9xx_update_plane(struct intel_plane *plane,
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		dspaddr_offset = plane_state->main.offset;
 	else
 		dspaddr_offset = linear_offset;
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 		/* pipesrc and dspsize control the size that is scaled from,
 		 * which should always be the user's requested size.
 		 */
@@ -3291,7 +3291,7 @@  static void i9xx_update_plane(struct intel_plane *plane,
 			      intel_plane_ggtt_offset(plane_state) +
 			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		I915_WRITE_FW(DSPSURF(i9xx_plane),
 			      intel_plane_ggtt_offset(plane_state) +
 			      dspaddr_offset);
@@ -3317,7 +3317,7 @@  static void i9xx_disable_plane(struct intel_plane *plane,
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
 	else
 		I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
@@ -3538,7 +3538,7 @@  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 	plane_ctl = PLANE_CTL_ENABLE;
 
-	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 9) && !IS_GEMINILAKE(dev_priv)) {
 		plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
 		plane_ctl |=
 			PLANE_CTL_PIPE_GAMMA_ENABLE |
@@ -3550,7 +3550,7 @@  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		plane_ctl |= cnl_plane_ctl_flip(rotation &
 						DRM_MODE_REFLECT_MASK);
 
@@ -3618,7 +3618,7 @@  __intel_display_resume(struct drm_device *dev,
 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 {
 	return intel_has_gpu_reset(dev_priv) &&
-		INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
+		IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv);
 }
 
 void intel_prepare_reset(struct drm_i915_private *dev_priv)
@@ -3757,7 +3757,7 @@  static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
 		   (new_crtc_state->pipe_src_h - 1));
 
 	/* on skylake this is done by detaching scalers */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		skl_detach_scalers(crtc);
 
 		if (new_crtc_state->pch_pfit.enabled)
@@ -4683,7 +4683,7 @@  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	 * Once NV12 is enabled, handle it here while allocating scaler
 	 * for NV12.
 	 */
-	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER) && crtc_state->base.enable &&
 	    need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
 		return -EINVAL;
@@ -5477,7 +5477,7 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (psl_clkgate_wa)
 		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		skylake_pfit_enable(intel_crtc);
 	else
 		ironlake_pfit_enable(intel_crtc);
@@ -5623,7 +5623,7 @@  static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		skylake_scaler_disable(intel_crtc);
 	else
 		ironlake_pfit_disable(intel_crtc, false);
@@ -6307,7 +6307,7 @@  static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* GDG double wide on either pipe, otherwise pipe A only */
-	return INTEL_GEN(dev_priv) < 4 &&
+	return IS_GEN(dev_priv, GEN_FOREVER, 3) &&
 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
 }
 
@@ -6367,7 +6367,7 @@  static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int clock_limit = dev_priv->max_dotclk_freq;
 
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
 
 		/*
@@ -6420,7 +6420,7 @@  static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 	 */
-	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
+	if ((IS_GEN(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) &&
 		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
 		return -EINVAL;
 
@@ -6577,7 +6577,7 @@  static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 	int pipe = crtc->pipe;
 	enum transcoder transcoder = crtc->config->cpu_transcoder;
 
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
@@ -6587,7 +6587,7 @@  static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 		 * registers are not unnecessarily accessed).
 		 */
 		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
-		    INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
+		    IS_GEN(dev_priv, GEN_FOREVER, 7)) && crtc->config->has_drrs) {
 			I915_WRITE(PIPE_DATA_M2(transcoder),
 					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -6971,7 +6971,7 @@  static void i9xx_compute_dpll(struct intel_crtc *crtc,
 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 		break;
 	}
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 
 	if (crtc_state->sdvo_tv_clock)
@@ -6985,7 +6985,7 @@  static void i9xx_compute_dpll(struct intel_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	crtc_state->dpll_hw_state.dpll = dpll;
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		crtc_state->dpll_hw_state.dpll_md = dpll_md;
@@ -7058,7 +7058,7 @@  static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
 			vsyncshift += adjusted_mode->crtc_htotal;
 	}
 
-	if (INTEL_GEN(dev_priv) > 3)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
 
 	I915_WRITE(HTOTAL(cpu_transcoder),
@@ -7217,7 +7217,7 @@  static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 	}
 
 	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
-		if (INTEL_GEN(dev_priv) < 4 ||
+		if (IS_GEN(dev_priv, GEN_FOREVER, 3) ||
 		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
 			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		else
@@ -7428,7 +7428,7 @@  static void i9xx_get_pfit_config(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t tmp;
 
-	if (INTEL_GEN(dev_priv) <= 3 &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3) &&
 	    (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
 		return;
 
@@ -7437,7 +7437,7 @@  static void i9xx_get_pfit_config(struct intel_crtc *crtc,
 		return;
 
 	/* Check whether the pfit is attached to our pipe. */
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 		if (crtc->pipe != PIPE_B)
 			return;
 	} else {
@@ -7506,7 +7506,7 @@  i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(i9xx_plane));
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		if (val & DISPPLANE_TILED) {
 			plane_config->tiling = I915_TILING_X;
 			fb->modifier = I915_FORMAT_MOD_X_TILED;
@@ -7520,7 +7520,7 @@  i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		offset = I915_READ(DSPOFFSET(i9xx_plane));
 		base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		if (plane_config->tiling)
 			offset = I915_READ(DSPTILEOFF(i9xx_plane));
 		else
@@ -7626,7 +7626,7 @@  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
 	intel_get_pipe_timings(crtc, pipe_config);
@@ -7634,7 +7634,7 @@  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
 	i9xx_get_pfit_config(crtc, pipe_config);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		/* No way to read it out on pipes B and C */
 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
 			tmp = dev_priv->chv_dpll_md[crtc->pipe];
@@ -8194,7 +8194,7 @@  static void haswell_set_pipemisc(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_crtc_state *config = intel_crtc->config;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
+	if (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		u32 val = 0;
 
 		switch (intel_crtc->config->pipe_bpp) {
@@ -8425,7 +8425,7 @@  static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
 		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
 		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
@@ -8437,7 +8437,7 @@  static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
 		 * gen < 8) and if DRRS is supported (to make sure the
 		 * registers are not unnecessarily read).
 		 */
-		if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
+		if (m2_n2 && IS_GEN(dev_priv, GEN_FOREVER, 7) &&
 			crtc->config->has_drrs) {
 			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
 			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
@@ -8536,12 +8536,12 @@  skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_CTL(pipe, plane_id));
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_GEN(dev_priv, 11, GEN_FOREVER))
 		pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
 	else
 		pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) {
 		alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
 		alpha &= PLANE_COLOR_ALPHA_MASK;
 	} else {
@@ -9188,7 +9188,7 @@  static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 	 * DDI E. So just check whether this pipe is wired to DDI E and whether
 	 * the PCH transcoder is on.
 	 */
-	if (INTEL_GEN(dev_priv) < 9 &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8) &&
 	    (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
 		pipe_config->has_pch_encoder = true;
 
@@ -9238,11 +9238,11 @@  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode =
 		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
+	if (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
 		bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
 
-		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
+		if (IS_GEMINILAKE(dev_priv) || IS_GEN(dev_priv, 10, GEN_FOREVER)) {
 			bool blend_mode_420 = tmp &
 					      PIPEMISC_YUV420_MODE_FULL_BLEND;
 
@@ -9258,7 +9258,7 @@  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
 	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 		power_domain_mask |= BIT_ULL(power_domain);
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			skylake_get_pfit_config(crtc, pipe_config);
 		else
 			ironlake_get_pfit_config(crtc, pipe_config);
@@ -10227,7 +10227,7 @@  int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 	struct drm_framebuffer *fb = plane_state->fb;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER) && plane->id != PLANE_CURSOR) {
 		ret = skl_update_scaler_plane(
 			to_intel_crtc_state(crtc_state),
 			to_intel_plane_state(plane_state));
@@ -10276,21 +10276,21 @@  int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 			 turn_off, turn_on, mode_changed);
 
 	if (turn_on) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+		if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv))
 			pipe_config->update_wm_pre = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->id != PLANE_CURSOR)
 			pipe_config->disable_cxsr = true;
 	} else if (turn_off) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+		if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv))
 			pipe_config->update_wm_post = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->id != PLANE_CURSOR)
 			pipe_config->disable_cxsr = true;
 	} else if (intel_wm_need_update(&plane->base, plane_state)) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv)) {
 			/* FIXME bollocks */
 			pipe_config->update_wm_pre = true;
 			pipe_config->update_wm_post = true;
@@ -10407,11 +10407,11 @@  static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 			return ret;
 		}
 	} else if (dev_priv->display.compute_intermediate_wm) {
-		if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
+		if (HAS_PCH_SPLIT(dev_priv) && IS_GEN(dev_priv, GEN_FOREVER, 8))
 			pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		if (mode_changed)
 			ret = skl_update_scaler_crtc(pipe_config);
 
@@ -10499,7 +10499,7 @@  compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
 	    IS_CHERRYVIEW(dev_priv)))
 		bpp = 10*3;
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		bpp = 12*3;
 	else
 		bpp = 8*3;
@@ -10641,7 +10641,7 @@  static void intel_dump_pipe_config(struct intel_crtc *crtc,
 		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,
 		      pipe_config->pixel_rate);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
 			      crtc->num_scalers,
 			      pipe_config->scaler_state.scaler_users,
@@ -10682,7 +10682,7 @@  static void intel_dump_pipe_config(struct intel_crtc *crtc,
 			      plane->base.id, plane->name,
 			      fb->base.id, fb->width, fb->height,
 			      drm_get_format_name(fb->format->format, &format_name));
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
 				      state->scaler_id,
 				      state->base.src.x1 >> 16,
@@ -11167,7 +11167,7 @@  intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 	PIPE_CONF_CHECK_I(lane_count);
 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-	if (INTEL_GEN(dev_priv) < 8) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 7)) {
 		PIPE_CONF_CHECK_M_N(dp_m_n);
 
 		if (current_config->has_drrs)
@@ -11193,7 +11193,7 @@  intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
-	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
+	if ((IS_GEN(dev_priv, GEN_FOREVER, 7) && !IS_HASWELL(dev_priv)) ||
 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		PIPE_CONF_CHECK_BOOL(limited_color_range);
 
@@ -11220,7 +11220,7 @@  intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_X(gmch_pfit.control);
 	/* pfit ratios are autocomputed by the hw on gen4+ */
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
 	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
 
@@ -11266,7 +11266,7 @@  intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
 	PIPE_CONF_CHECK_X(dsi_pll.div);
 
-	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
+	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5, GEN_FOREVER))
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
 	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
@@ -11316,7 +11316,7 @@  static void verify_wm_state(struct drm_crtc *crtc,
 	const enum pipe pipe = intel_crtc->pipe;
 	int plane, level, max_level = ilk_wm_max_level(dev_priv);
 
-	if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8) || !new_state->active)
 		return;
 
 	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
@@ -12293,7 +12293,7 @@  static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 				 *
 				 * No clue what this is supposed to achieve.
 				 */
-				if (INTEL_GEN(dev_priv) >= 9)
+				if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 					dev_priv->display.initial_watermarks(intel_state,
 									     to_intel_crtc_state(new_crtc_state));
 			}
@@ -12485,7 +12485,7 @@  static int intel_atomic_commit(struct drm_device *dev,
 	 * FIXME doing watermarks and fb cleanup from a vblank worker
 	 * (assuming we had any) would solve these problems.
 	 */
-	if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8) && state->legacy_cursor_update) {
 		struct intel_crtc_state *new_crtc_state;
 		struct intel_crtc *crtc;
 		int i;
@@ -12592,7 +12592,7 @@  static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
 	if (!dma_fence_is_i915(fence))
 		return;
 
-	if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+	if (IS_GEN(to_i915(crtc->dev), GEN_FOREVER, 5))
 		return;
 
 	if (drm_crtc_vblank_get(crtc))
@@ -12770,7 +12770,7 @@  skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
 	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEMINILAKE(dev_priv) || IS_GEN(dev_priv, 10, GEN_FOREVER))
 		max_dotclk *= 2;
 
 	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
@@ -12801,7 +12801,7 @@  intel_check_primary_plane(struct intel_plane *plane,
 	struct drm_rect clip = {};
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		/* use scaler when colorkey is not required */
 		if (!state->ckey.flags) {
 			min_scale = 1;
@@ -12825,7 +12825,7 @@  intel_check_primary_plane(struct intel_plane *plane,
 	if (!state->base.fb)
 		return 0;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		ret = skl_check_plane_surface(crtc_state, state);
 		if (ret)
 			return ret;
@@ -12839,7 +12839,7 @@  intel_check_primary_plane(struct intel_plane *plane,
 		state->ctl = i9xx_plane_ctl(crtc_state, state);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv))
 		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
 
 	return 0;
@@ -12874,7 +12874,7 @@  static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 
 	if (intel_cstate->update_pipe)
 		intel_update_pipe_config(old_intel_cstate, intel_cstate);
-	else if (INTEL_GEN(dev_priv) >= 9)
+	else if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		skl_detach_scalers(intel_crtc);
 
 out:
@@ -12998,9 +12998,9 @@  static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
 	    modifier != DRM_FORMAT_MOD_LINEAR)
 		return false;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return skl_mod_supported(format, modifier);
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		return i965_mod_supported(format, modifier);
 	else
 		return i8xx_mod_supported(format, modifier);
@@ -13197,7 +13197,7 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 	primary->can_scale = false;
 	primary->max_downscale = 1;
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		primary->can_scale = true;
 		state->scaler_id = -1;
 	}
@@ -13206,7 +13206,7 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
 	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
 	 */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
+	if (HAS_FBC(dev_priv) && IS_GEN(dev_priv, GEN_FOREVER, 3))
 		primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
 	else
 		primary->i9xx_plane = (enum i9xx_plane_id) pipe;
@@ -13214,7 +13214,7 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
 	primary->check_plane = intel_check_primary_plane;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
 
@@ -13226,7 +13226,7 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		primary->update_plane = skl_update_plane;
 		primary->disable_plane = skl_disable_plane;
 		primary->get_hw_state = skl_plane_get_hw_state;
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
 		modifiers = i9xx_format_modifiers;
@@ -13244,14 +13244,14 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		primary->get_hw_state = i9xx_plane_get_hw_state;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
 					       0, &intel_plane_funcs,
 					       intel_primary_formats, num_formats,
 					       modifiers,
 					       DRM_PLANE_TYPE_PRIMARY,
 					       "plane 1%c", pipe_name(pipe));
-	else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+	else if (IS_GEN(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv))
 		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
 					       0, &intel_plane_funcs,
 					       intel_primary_formats, num_formats,
@@ -13269,12 +13269,12 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	if (ret)
 		goto fail;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
 			DRM_MODE_REFLECT_X;
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
@@ -13282,14 +13282,14 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
 			DRM_MODE_REFLECT_X;
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
 	} else {
 		supported_rotations = DRM_MODE_ROTATE_0;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		drm_plane_create_rotation_property(&primary->base,
 						   DRM_MODE_ROTATE_0,
 						   supported_rotations);
@@ -13362,13 +13362,13 @@  intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 	if (ret)
 		goto fail;
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		drm_plane_create_rotation_property(&cursor->base,
 						   DRM_MODE_ROTATE_0,
 						   DRM_MODE_ROTATE_0 |
 						   DRM_MODE_ROTATE_180);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		state->scaler_id = -1;
 
 	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
@@ -13548,7 +13548,7 @@  static bool has_edp_a(struct drm_i915_private *dev_priv)
 
 static bool intel_crt_present(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return false;
 
 	if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
@@ -13929,7 +13929,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
-		if (INTEL_GEN(dev_priv) < 9) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 8)) {
 			DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
 				      mode_cmd->modifier[0]);
 			goto err;
@@ -13947,7 +13947,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	 * gen2/3 display engine uses the fence if present,
 	 * so the tiling mode must match the fb modifier exactly.
 	 */
-	if (INTEL_GEN(dev_priv) < 4 &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3) &&
 	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 		DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
 		goto err;
@@ -13981,7 +13981,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	case DRM_FORMAT_ARGB8888:
 		break;
 	case DRM_FORMAT_XRGB1555:
-		if (INTEL_GEN(dev_priv) > 3) {
+		if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -13989,7 +13989,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		break;
 	case DRM_FORMAT_ABGR8888:
 		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
-		    INTEL_GEN(dev_priv) < 9) {
+		    IS_GEN(dev_priv, GEN_FOREVER, 8)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -13998,7 +13998,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
-		if (INTEL_GEN(dev_priv) < 4) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -14015,7 +14015,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_VYUY:
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -14162,7 +14162,7 @@  void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 {
 	intel_init_cdclk_hooks(dev_priv);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			skylake_get_initial_plane_config;
@@ -14241,7 +14241,7 @@  void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		dev_priv->display.update_crtcs = skl_update_crtcs;
 	else
 		dev_priv->display.update_crtcs = intel_update_crtcs;
@@ -14774,7 +14774,7 @@  intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
 {
 	struct intel_crtc *crtc;
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		return;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -15210,7 +15210,7 @@  intel_modeset_setup_hw_state(struct drm_device *dev,
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		vlv_wm_get_hw_state(dev);
 		vlv_wm_sanitize(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		skl_wm_get_hw_state(dev);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_wm_get_hw_state(dev);
@@ -15361,7 +15361,7 @@  void intel_connector_attach_encoder(struct intel_connector *connector,
  */
 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
 {
-	unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
+	unsigned reg = IS_GEN(dev_priv, 6, GEN_FOREVER) ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
 	u16 gmch_ctrl;
 
 	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
@@ -15467,13 +15467,13 @@  intel_display_capture_error_state(struct drm_i915_private *dev_priv)
 
 		error->plane[i].control = I915_READ(DSPCNTR(i));
 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
-		if (INTEL_GEN(dev_priv) <= 3) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 			error->plane[i].size = I915_READ(DSPSIZE(i));
 			error->plane[i].pos = I915_READ(DSPPOS(i));
 		}
-		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
+		if (IS_GEN(dev_priv, GEN_FOREVER, 7) && !IS_HASWELL(dev_priv))
 			error->plane[i].addr = I915_READ(DSPADDR(i));
-		if (INTEL_GEN(dev_priv) >= 4) {
+		if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 			error->plane[i].surface = I915_READ(DSPSURF(i));
 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
 		}
@@ -15538,13 +15538,13 @@  intel_display_print_error_state(struct drm_i915_error_state_buf *m,
 		err_printf(m, "Plane [%d]:\n", i);
 		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
 		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
-		if (INTEL_GEN(dev_priv) <= 3) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
 			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
 		}
-		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
+		if (IS_GEN(dev_priv, GEN_FOREVER, 7) && !IS_HASWELL(dev_priv))
 			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
-		if (INTEL_GEN(dev_priv) >= 4) {
+		if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
 			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
 		}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index abbe1e4e0af5..4534afe4fe18 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1467,7 +1467,7 @@  static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				    enum port port)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return skl_aux_ctl_reg(dev_priv, port);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return ilk_aux_ctl_reg(dev_priv, port);
@@ -1478,7 +1478,7 @@  static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
 				     enum port port, int index)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return skl_aux_data_reg(dev_priv, port, index);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return ilk_aux_data_reg(dev_priv, port, index);
@@ -1726,7 +1726,7 @@  intel_dp_compute_config(struct intel_encoder *encoder,
 
 		intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
-		if (INTEL_GEN(dev_priv) >= 9) {
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 			int ret;
 			ret = skl_update_scaler_crtc(pipe_config);
 			if (ret)
@@ -3208,7 +3208,7 @@  intel_dp_voltage_max(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 		return intel_ddi_dp_voltage_max(encoder);
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -3227,7 +3227,7 @@  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -3760,7 +3760,7 @@  intel_edp_init_dpcd(struct intel_dp *intel_dp)
 		DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9 &&
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER) &&
 	    (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
 		uint8_t frame_sync_cap;
 
@@ -5468,10 +5468,10 @@  bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
 	 * eDP not supported on g4x. so bail out early just
 	 * for a bit extra safety in case the VBT is bonkers.
 	 */
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		return false;
 
-	if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8) && port == PORT_A)
 		return true;
 
 	return intel_bios_is_port_edp(dev_priv, port);
@@ -5830,7 +5830,7 @@  static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER) && !IS_CHERRYVIEW(dev_priv)) {
 		switch (index) {
 		case DRRS_HIGH_RR:
 			intel_dp_set_m_n(intel_crtc, M1_N1);
@@ -5842,7 +5842,7 @@  static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 		default:
 			DRM_ERROR("Unsupported refreshrate type\n");
 		}
-	} else if (INTEL_GEN(dev_priv) > 6) {
+	} else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
 		u32 val;
 
@@ -6115,7 +6115,7 @@  intel_dp_drrs_init(struct intel_connector *connector,
 	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
 	mutex_init(&dev_priv->drrs.mutex);
 
-	if (INTEL_GEN(dev_priv) <= 6) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6)) {
 		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
 		return NULL;
 	}
@@ -6353,7 +6353,7 @@  intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->active_pipe = INVALID_PIPE;
 
 	/* intel_dp vfuncs */
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
@@ -6362,7 +6362,7 @@  intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	else
 		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
 	else
 		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
@@ -6501,7 +6501,7 @@  bool intel_dp_init(struct drm_i915_private *dev_priv,
 		intel_encoder->enable = vlv_enable_dp;
 		intel_encoder->disable = vlv_disable_dp;
 		intel_encoder->post_disable = vlv_post_disable_dp;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		intel_encoder->pre_enable = g4x_pre_enable_dp;
 		intel_encoder->enable = g4x_enable_dp;
 		intel_encoder->disable = ilk_disable_dp;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 51c5ae4e9116..70743bf7e074 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -210,7 +210,7 @@  void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
 
 	/* PCH only available on ILK+ */
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		return;
 
 	if (pll == NULL)
@@ -1860,7 +1860,7 @@  static void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (INTEL_GEN(dev_priv) < 9) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8)) {
 		uint32_t val = I915_READ(LCPLL_CTL);
 
 		/*
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0ad9184eba97..32a1fee719a0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -193,7 +193,7 @@  __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 	case VIDEO_DECODE_CLASS:
 	case VIDEO_ENHANCEMENT_CLASS:
 	case COPY_ENGINE_CLASS:
-		if (INTEL_GEN(dev_priv) < 8)
+		if (IS_GEN(dev_priv, GEN_FOREVER, 7))
 			return 0;
 		return GEN8_LR_CONTEXT_OTHER_SIZE;
 	}
@@ -696,10 +696,10 @@  u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	u64 acthd;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 					 RING_ACTHD_UDW(engine->mmio_base));
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 	else
 		acthd = I915_READ(ACTHD);
@@ -712,7 +712,7 @@  u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	u64 bbaddr;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
 					  RING_BBADDR_UDW(engine->mmio_base));
 	else
@@ -1472,7 +1472,7 @@  static bool ring_is_idle(struct intel_engine_cs *engine)
 		idle = false;
 
 	/* No bit for gen2, so assume the CS parser is idle */
-	if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
+	if (IS_GEN(dev_priv, 3, GEN_FOREVER) && !(I915_READ_MODE(engine) & MODE_IDLE))
 		idle = false;
 
 	intel_runtime_pm_put(dev_priv);
@@ -1773,7 +1773,7 @@  void intel_engine_dump(struct intel_engine_cs *engine,
 	drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
 		   I915_READ(RING_CTL(engine->mmio_base)),
 		   I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
-	if (INTEL_GEN(engine->i915) > 2) {
+	if (IS_GEN(engine->i915, 3, GEN_FOREVER)) {
 		drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
 			   I915_READ(RING_MI_MODE(engine->mmio_base)),
 			   I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
@@ -1796,16 +1796,16 @@  void intel_engine_dump(struct intel_engine_cs *engine,
 	addr = intel_engine_get_last_batch_head(engine);
 	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
 		   upper_32_bits(addr), lower_32_bits(addr));
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
 					RING_DMA_FADD_UDW(engine->mmio_base));
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
 	else
 		addr = I915_READ(DMA_FADD_I8XX);
 	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
 		   upper_32_bits(addr), lower_32_bits(addr));
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		drm_printf(m, "\tIPEIR: 0x%08x\n",
 			   I915_READ(RING_IPEIR(engine->mmio_base)));
 		drm_printf(m, "\tIPEHR: 0x%08x\n",
@@ -1865,7 +1865,7 @@  void intel_engine_dump(struct intel_engine_cs *engine,
 		}
 		drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
 		rcu_read_unlock();
-	} else if (INTEL_GEN(dev_priv) > 6) {
+	} else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
 			   I915_READ(RING_PP_DIR_BASE(engine)));
 		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
@@ -1895,7 +1895,7 @@  void intel_engine_dump(struct intel_engine_cs *engine,
 	}
 	spin_unlock_irq(&b->rb_lock);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0ad854095c38..791c77044460 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -48,17 +48,17 @@  static inline bool fbc_supported(struct drm_i915_private *dev_priv)
 
 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
 {
-	return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
+	return IS_HASWELL(dev_priv) || IS_GEN(dev_priv, 8, GEN_FOREVER);
 }
 
 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) < 4;
+	return IS_GEN(dev_priv, GEN_FOREVER, 3);
 }
 
 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) <= 3;
+	return IS_GEN(dev_priv, GEN_FOREVER, 3);
 }
 
 /*
@@ -96,7 +96,7 @@  static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 	intel_fbc_get_plane_source_size(cache, NULL, &lines);
 	if (IS_GEN7(dev_priv))
 		lines = min(lines, 2048);
-	else if (INTEL_GEN(dev_priv) >= 8)
+	else if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		lines = min(lines, 2560);
 
 	/* Hardware needs the full buffer stride, not just the active area. */
@@ -357,7 +357,7 @@  static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 
 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		return ilk_fbc_is_active(dev_priv);
 	else if (IS_GM45(dev_priv))
 		return g4x_fbc_is_active(dev_priv);
@@ -371,9 +371,9 @@  static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 
 	fbc->active = true;
 
-	if (INTEL_GEN(dev_priv) >= 7)
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		gen7_fbc_activate(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		ilk_fbc_activate(dev_priv);
 	else if (IS_GM45(dev_priv))
 		g4x_fbc_activate(dev_priv);
@@ -387,7 +387,7 @@  static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 
 	fbc->active = false;
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		ilk_fbc_deactivate(dev_priv);
 	else if (IS_GM45(dev_priv))
 		g4x_fbc_deactivate(dev_priv);
@@ -568,7 +568,7 @@  static int find_compression_threshold(struct drm_i915_private *dev_priv,
 
 	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 						   4096, 0, end);
-	if (ret && INTEL_GEN(dev_priv) <= 4) {
+	if (ret && IS_GEN(dev_priv, GEN_FOREVER, 4)) {
 		return 0;
 	} else if (ret) {
 		compression_threshold <<= 1;
@@ -601,7 +601,7 @@  static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 
 	fbc->threshold = ret;
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 	else if (IS_GM45(dev_priv)) {
 		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
@@ -724,10 +724,10 @@  static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 	struct intel_fbc *fbc = &dev_priv->fbc;
 	unsigned int effective_w, effective_h, max_w, max_h;
 
-	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv)) {
 		max_w = 4096;
 		max_h = 4096;
-	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		max_w = 4096;
 		max_h = 2048;
 	} else {
@@ -820,7 +820,7 @@  static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 		return false;
 	}
-	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_G4X(dev_priv) &&
 	    cache->plane.rotation != DRM_MODE_ROTATE_0) {
 		fbc->no_fbc_reason = "rotation unsupported";
 		return false;
@@ -1325,7 +1325,7 @@  static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
 	if (!HAS_FBC(dev_priv))
 		return 0;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+	if (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return 1;
 
 	return 0;
@@ -1382,7 +1382,7 @@  void intel_fbc_init(struct drm_i915_private *dev_priv)
 	}
 
 	/* This value was pulled out of someone's hat */
-	if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) && !IS_GM45(dev_priv))
 		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
 
 	/* We still don't have any sort of hardware state readout for FBC, so
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 77c123cc8817..3d683a6a0849 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -264,7 +264,7 @@  static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev_priv))
 		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
-	else if (INTEL_GEN(dev_priv) >= 8)
+	else if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 
 	return old;
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 42e45ae87393..769121688e51 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -97,7 +97,7 @@  semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
 	 * ringbuffer itself.
 	 */
 	head = I915_READ_HEAD(engine) & HEAD_ADDR;
-	backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
+	backwards = (IS_GEN(dev_priv, 8, GEN_FOREVER)) ? 5 : 4;
 	vaddr = (void __iomem *)engine->buffer->vaddr;
 
 	for (i = backwards; i; --i) {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..ed1612c97d74 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -651,7 +651,7 @@  static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
 	/* PORT E doesn't have HDCP, and PORT F is disabled */
-	return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
+	return ((IS_GEN(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv)) &&
 		!IS_CHERRYVIEW(dev_priv) && port < PORT_E);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f5d7bfb43006..d436ada23619 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1481,11 +1481,11 @@  static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
 		&dev_priv->vbt.ddi_port_info[encoder->port];
 	int max_tmds_clock;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv))
 		max_tmds_clock = 594000;
-	else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
+	else if (IS_GEN(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv))
 		max_tmds_clock = 300000;
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN(dev_priv, 5, GEN_FOREVER))
 		max_tmds_clock = 225000;
 	else
 		max_tmds_clock = 165000;
@@ -1754,7 +1754,7 @@  bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 
 	pipe_config->lane_count = 4;
 
-	if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
+	if (scdc->scrambling.supported && (IS_GEN(dev_priv, 10, GEN_FOREVER) ||
 					   IS_GEMINILAKE(dev_priv))) {
 		if (scdc->scrambling.low_rates)
 			pipe_config->hdmi_scrambling = true;
@@ -2324,7 +2324,7 @@  void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 	connector->doublescan_allowed = 0;
 	connector->stereo_allowed = 1;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv))
 		connector->ycbcr_420_allowed = true;
 
 	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2c8380a0121..55df19ec879e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1488,7 +1488,7 @@  static void enable_execlists(struct intel_engine_cs *engine)
 	 * deeper FIFO it's not needed and it's not worth adding
 	 * more statements to the irq handler to support it.
 	 */
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_GEN(dev_priv, 11, GEN_FOREVER))
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
 	else
@@ -2068,7 +2068,7 @@  int logical_render_ring_init(struct intel_engine_cs *engine)
 		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
 	/* Override some for render ring. */
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		engine->init_hw = gen9_init_render_ring;
 	else
 		engine->init_hw = gen8_init_render_ring;
@@ -2111,7 +2111,7 @@  make_rpcs(struct drm_i915_private *dev_priv)
 	 * No explicit RPCS request is needed to ensure full
 	 * slice/subslice/EU enablement prior to Gen9.
 	*/
-	if (INTEL_GEN(dev_priv) < 9)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8))
 		return 0;
 
 	/*
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 4677ac0b10d7..8d59feec9049 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -139,12 +139,12 @@  static void intel_lvds_get_config(struct intel_encoder *encoder,
 
 	pipe_config->base.adjusted_mode.flags |= flags;
 
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		pipe_config->gmch_pfit.lvds_border_bits =
 			tmp & LVDS_BORDER_ENABLE;
 
 	/* gen2/3 store dither state in pfit control, needs to match */
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3)) {
 		tmp = I915_READ(PFIT_CONTROL);
 
 		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
@@ -189,7 +189,7 @@  static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 	/* Convert from 100ms to 100us units */
 	pps->t4 = val * 1000;
 
-	if (INTEL_GEN(dev_priv) <= 4 &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) &&
 	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 		DRM_DEBUG_KMS("Panel power timings uninitialized, "
 			      "setting defaults\n");
@@ -396,7 +396,7 @@  static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 	unsigned int lvds_bpp;
 
 	/* Should never happen!! */
-	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3) && intel_crtc->pipe == 0) {
 		DRM_ERROR("Can't support LVDS on pipe A\n");
 		return false;
 	}
@@ -914,7 +914,7 @@  static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 
 	/* Otherwise LVDS was only attached to mobile products,
 	 * except for the inglorious 830gm */
-	if (INTEL_GEN(dev_priv) <= 4 &&
+	if (IS_GEN(dev_priv, GEN_FOREVER, 4) &&
 	    IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 		return true;
 
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index abb7a8c1e340..4db2ed80dfa5 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -187,7 +187,7 @@  static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 		table->table = broxton_mocs_table;
 		result = true;
 	} else {
-		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
+		WARN_ONCE(IS_GEN(dev_priv, 9, GEN_FOREVER),
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 41e9465d44a8..8cff693b2c4c 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -945,7 +945,7 @@  static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 	/* XXX: This is not the same logic as in the xorg driver, but more in
 	 * line with the intel documentation for the i965
 	 */
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		/* on i965 use the PGM reg to read out the autoscaler values */
 		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 78a53c8b1789..9900a1f5ab23 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -326,7 +326,7 @@  void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 		break;
 	case DRM_MODE_SCALE_ASPECT:
 		/* Scale but preserve the aspect ratio */
-		if (INTEL_GEN(dev_priv) >= 4)
+		if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 			i965_scale_aspect(pipe_config, &pfit_control);
 		else
 			i9xx_scale_aspect(pipe_config, &pfit_control,
@@ -340,7 +340,7 @@  void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 		if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
 		    pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
 			pfit_control |= PFIT_ENABLE;
-			if (INTEL_GEN(dev_priv) >= 4)
+			if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 				pfit_control |= PFIT_SCALING_AUTO;
 			else
 				pfit_control |= (VERT_AUTO_SCALE |
@@ -356,7 +356,7 @@  void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 
 	/* 965+ wants fuzzy fitting */
 	/* FIXME: handle multiple panels by failing gracefully */
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
 				 PFIT_FILTER_FUZZY);
 
@@ -367,7 +367,7 @@  void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 	}
 
 	/* Make sure pre-965 set dither correctly for 18bpp panels. */
-	if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3) && pipe_config->pipe_bpp == 18)
 		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
 
 	pipe_config->gmch_pfit.control = pfit_control;
@@ -497,7 +497,7 @@  static u32 i9xx_get_backlight(struct intel_connector *connector)
 	u32 val;
 
 	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 		val >>= 1;
 
 	if (panel->backlight.combination_mode) {
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 1f5cd572a7ff..d33b65cf26c0 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -604,7 +604,7 @@  static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 {
 	if (IS_GEN2(dev_priv))
 		return i8xx_pipe_crc_ctl_reg(source, val);
-	else if (INTEL_GEN(dev_priv) < 5)
+	else if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b026b020d8b8..f3cbbc28237b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2571,9 +2571,9 @@  static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
 static unsigned int
 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		return 3072;
-	else if (INTEL_GEN(dev_priv) >= 7)
+	else if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		return 768;
 	else
 		return 512;
@@ -2583,10 +2583,10 @@  static unsigned int
 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
 		     int level, bool is_sprite)
 {
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		/* BDW primary/sprite plane watermarks */
 		return level == 0 ? 255 : 2047;
-	else if (INTEL_GEN(dev_priv) >= 7)
+	else if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		/* IVB/HSW primary/sprite plane watermarks */
 		return level == 0 ? 127 : 1023;
 	else if (!is_sprite)
@@ -2600,7 +2600,7 @@  ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
 static unsigned int
 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
 {
-	if (INTEL_GEN(dev_priv) >= 7)
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		return level == 0 ? 63 : 255;
 	else
 		return level == 0 ? 31 : 63;
@@ -2608,7 +2608,7 @@  ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
 
 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		return 31;
 	else
 		return 15;
@@ -2637,7 +2637,7 @@  static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
 		 * FIFO size is only half of the self
 		 * refresh FIFO size on ILK/SNB.
 		 */
-		if (INTEL_GEN(dev_priv) <= 6)
+		if (IS_GEN(dev_priv, GEN_FOREVER, 6))
 			fifo_size /= 2;
 	}
 
@@ -2798,7 +2798,7 @@  hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 				  uint16_t wm[8])
 {
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		uint32_t val;
 		int ret, i;
 		int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2883,14 +2883,14 @@  static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 		wm[2] = (sskpd >> 12) & 0xFF;
 		wm[3] = (sskpd >> 20) & 0x1FF;
 		wm[4] = (sskpd >> 32) & 0x1FF;
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		uint32_t sskpd = I915_READ(MCH_SSKPD);
 
 		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
 		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
 		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
 		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		uint32_t mltr = I915_READ(MLTR_ILK);
 
 		/* ILK primary LP0 latency is 700 ns */
@@ -2925,11 +2925,11 @@  static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
 {
 	/* how many WM levels are we expecting */
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return 7;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		return 4;
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		return 3;
 	else
 		return 2;
@@ -2954,7 +2954,7 @@  static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
 		 * - latencies are in us on gen9.
 		 * - before then, WM1+ latency values are in 0.5us units
 		 */
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			latency *= 10;
 		else if (level > 0)
 			latency *= 5;
@@ -3090,7 +3090,7 @@  static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
 	usable_level = max_level;
 
 	/* ILK/SNB: LP2+ watermarks only w/o sprites */
-	if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 6) && pipe_wm->sprites_enabled)
 		usable_level = 1;
 
 	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -3235,12 +3235,12 @@  static void ilk_wm_merge(struct drm_device *dev,
 	int last_enabled_level = max_level;
 
 	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
-	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
+	if ((IS_GEN(dev_priv, GEN_FOREVER, 6) || IS_IVYBRIDGE(dev_priv)) &&
 	    config->num_pipes_active > 1)
 		last_enabled_level = 0;
 
 	/* ILK: FBC WM must be disabled always */
-	merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
+	merged->fbc_wm_enabled = IS_GEN(dev_priv, 6, GEN_FOREVER);
 
 	/* merge each WM1+ level */
 	for (level = 1; level <= max_level; level++) {
@@ -3330,7 +3330,7 @@  static void ilk_compute_wm_results(struct drm_device *dev,
 		if (r->enable)
 			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
 
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 			results->wm_lp[wm_lp - 1] |=
 				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
 		else
@@ -3341,7 +3341,7 @@  static void ilk_compute_wm_results(struct drm_device *dev,
 		 * Always set WM1S_LP_EN when spr_val != 0, even if the
 		 * level is disabled. Doing otherwise could cause underruns.
 		 */
-		if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 6) && r->spr_val) {
 			WARN_ON(wm_lp != 1);
 			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
 		} else
@@ -3546,7 +3546,7 @@  static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
 		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
 
-	if (INTEL_GEN(dev_priv) >= 7) {
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
 			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
 		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
@@ -3785,7 +3785,7 @@  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
 	WARN_ON(ddb_size == 0);
 
-	if (INTEL_GEN(dev_priv) < 11)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 10))
 		ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
 	/*
@@ -3996,7 +3996,7 @@  int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEMINILAKE(dev_priv) || IS_GEN(dev_priv, 10, GEN_FOREVER))
 		dotclk *= 2;
 
 	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
@@ -4330,7 +4330,7 @@  skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
 	wm_intermediate_val = latency * pixel_rate * cpp;
 	ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		ret = add_fixed16_u32(ret, 1);
 
 	return ret;
@@ -4438,7 +4438,7 @@  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
-	if (INTEL_GEN(dev_priv) >= 11 &&
+	if (IS_GEN(dev_priv, 11, GEN_FOREVER) &&
 	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
 		wp->dbuf_block_size = 256;
 	else
@@ -4473,7 +4473,7 @@  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 					   wp->y_min_scanlines,
 					   wp->dbuf_block_size);
 
-		if (INTEL_GEN(dev_priv) >= 10)
+		if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 			interm_pbpl++;
 
 		wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
@@ -4573,7 +4573,7 @@  static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (IS_GEN(dev_priv, 11, GEN_FOREVER)) {
 		if (wp->y_tiled) {
 			uint32_t extra_lines;
 			uint_fixed_16_16_t fp_min_disp_buf_needed;
@@ -4705,14 +4705,14 @@  static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
 		goto exit;
 
 	/* Transition WM are not recommended by HW team for GEN9 */
-	if (INTEL_GEN(dev_priv) <= 9)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 9))
 		goto exit;
 
 	/* Transition WM don't make any sense if ipc is disabled */
 	if (!dev_priv->ipc_enabled)
 		goto exit;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		trans_min = 4;
 
 	trans_offset_b = trans_min + trans_amount;
@@ -4835,7 +4835,7 @@  static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 
 	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
 			    &ddb->plane[pipe][plane_id]);
-	if (INTEL_GEN(dev_priv) < 11)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 10))
 		skl_ddb_entry_write(dev_priv,
 				    PLANE_NV12_BUF_CFG(pipe, plane_id),
 				    &ddb->y_plane[pipe][plane_id]);
@@ -5249,7 +5249,7 @@  static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
 	ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
 
 	/* 5/6 split only in single pipe config on IVB+ */
-	if (INTEL_GEN(dev_priv) >= 7 &&
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER) &&
 	    config.num_pipes_active == 1 && config.sprites_enabled) {
 		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
 		ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
@@ -5848,7 +5848,7 @@  void ilk_wm_get_hw_state(struct drm_device *dev)
 	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
 
 	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
-	if (INTEL_GEN(dev_priv) >= 7) {
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
 		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
 	}
@@ -6076,7 +6076,7 @@  static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		limits = (rps->max_freq_softlimit) << 23;
 		if (val <= rps->min_freq_softlimit)
 			limits |= (rps->min_freq_softlimit) << 14;
@@ -6222,7 +6222,7 @@  static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
 	if (val != rps->cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   GEN9_FREQUENCY(val));
 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -6653,7 +6653,7 @@  static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	/* 2b: Program RC6 thresholds.*/
-	if (INTEL_GEN(dev_priv) >= 10) {
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER)) {
 		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
 		I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
 	} else if (IS_SKYLAKE(dev_priv)) {
@@ -6943,7 +6943,7 @@  static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 			 * No floor required for ring frequency on SKL.
 			 */
 			ring_freq = gpu_freq;
-		} else if (INTEL_GEN(dev_priv) >= 8) {
+		} else if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev_priv)) {
@@ -7960,7 +7960,7 @@  void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 		cherryview_init_gt_powersave(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_init_gt_powersave(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_init_rps_frequencies(dev_priv);
 
 	/* Derive initial user preferences/limits from the hardware limits */
@@ -8015,7 +8015,7 @@  void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
  */
 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5))
 		return;
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
@@ -8049,13 +8049,13 @@  static void intel_disable_rc6(struct drm_i915_private *dev_priv)
 	if (!dev_priv->gt_pm.rc6.enabled)
 		return;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		gen9_disable_rc6(dev_priv);
 	else if (IS_CHERRYVIEW(dev_priv))
 		cherryview_disable_rc6(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_disable_rc6(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_disable_rc6(dev_priv);
 
 	dev_priv->gt_pm.rc6.enabled = false;
@@ -8068,13 +8068,13 @@  static void intel_disable_rps(struct drm_i915_private *dev_priv)
 	if (!dev_priv->gt_pm.rps.enabled)
 		return;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		gen9_disable_rps(dev_priv);
 	else if (IS_CHERRYVIEW(dev_priv))
 		cherryview_disable_rps(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_disable_rps(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_disable_rps(dev_priv);
 	else if (IS_IRONLAKE_M(dev_priv))
 		ironlake_disable_drps(dev_priv);
@@ -8117,11 +8117,11 @@  static void intel_enable_rc6(struct drm_i915_private *dev_priv)
 		cherryview_enable_rc6(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_enable_rc6(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 9)
+	else if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		gen9_enable_rc6(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		gen8_enable_rc6(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		gen6_enable_rc6(dev_priv);
 
 	dev_priv->gt_pm.rc6.enabled = true;
@@ -8140,11 +8140,11 @@  static void intel_enable_rps(struct drm_i915_private *dev_priv)
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		gen6_enable_rps(dev_priv);
 	} else if (IS_IRONLAKE_M(dev_priv)) {
 		ironlake_enable_drps(dev_priv);
@@ -9059,7 +9059,7 @@  void intel_init_pm(struct drm_i915_private *dev_priv)
 		i915_ironlake_get_mem_freq(dev_priv);
 
 	/* For FIFO watermark updates */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		skl_setup_wm_latency(dev_priv);
 		dev_priv->display.initial_watermarks = skl_initial_wm;
 		dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
@@ -9205,7 +9205,7 @@  int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
 	*val = I915_READ_FW(GEN6_PCODE_DATA);
 	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
 
-	if (INTEL_GEN(dev_priv) > 6)
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		status = gen7_check_mailbox_status(dev_priv);
 	else
 		status = gen6_check_mailbox_status(dev_priv);
@@ -9253,7 +9253,7 @@  int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
 
 	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
 
-	if (INTEL_GEN(dev_priv) > 6)
+	if (IS_GEN(dev_priv, 7, GEN_FOREVER))
 		status = gen7_check_mailbox_status(dev_priv);
 	else
 		status = gen6_check_mailbox_status(dev_priv);
@@ -9382,7 +9382,7 @@  static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
 					 GEN9_FREQ_SCALER);
 	else if (IS_CHERRYVIEW(dev_priv))
@@ -9395,7 +9395,7 @@  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
 					 GT_FREQUENCY_MULTIPLIER);
 	else if (IS_CHERRYVIEW(dev_priv))
@@ -9496,7 +9496,7 @@  u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
 {
 	u32 cagf;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ef374f936b9..b97a7bdab1d0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -126,7 +126,7 @@  static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				       enum port port)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return DP_AUX_CH_CTL(port);
 	else
 		return EDP_PSR_AUX_CTL;
@@ -135,7 +135,7 @@  static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 					enum port port, int index)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return DP_AUX_CH_DATA(port, index);
 	else
 		return EDP_PSR_AUX_DATA(index);
@@ -521,7 +521,7 @@  void intel_psr_enable(struct intel_dp *intel_dp,
 	dev_priv->psr.enable_source(intel_dp, crtc_state);
 	dev_priv->psr.enabled = intel_dp;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		intel_psr_activate(intel_dp);
 	} else {
 		/*
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5718f37160c5..1bd37d8cedf4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -346,7 +346,7 @@  static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	u32 addr;
 
 	addr = dev_priv->status_page_dmah->busaddr;
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 	I915_WRITE(HWS_PGA, addr);
 }
@@ -386,7 +386,7 @@  static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		mmio = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 
 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
@@ -414,7 +414,7 @@  static bool stop_ring(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	if (INTEL_GEN(dev_priv) > 2) {
+	if (IS_GEN(dev_priv, 3, GEN_FOREVER)) {
 		I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 		if (intel_wait_for_register(dev_priv,
 					    RING_MI_MODE(engine->mmio_base),
@@ -521,7 +521,7 @@  static int init_ring_common(struct intel_engine_cs *engine)
 
 	intel_engine_init_hangcheck(engine);
 
-	if (INTEL_GEN(dev_priv) > 2)
+	if (IS_GEN(dev_priv, 3, GEN_FOREVER))
 		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 
 out:
@@ -655,7 +655,7 @@  static int init_render_ring(struct intel_engine_cs *engine)
 	if (IS_GEN(dev_priv, 6, 7))
 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 
 	return init_workarounds_ring(engine);
@@ -1352,7 +1352,7 @@  void intel_engine_cleanup(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	WARN_ON(INTEL_GEN(dev_priv) > 2 &&
+	WARN_ON(IS_GEN(dev_priv, 3, GEN_FOREVER) &&
 		(I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
 	intel_ring_unpin(engine->buffer);
@@ -1892,7 +1892,7 @@  static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
 	if (!HAS_LEGACY_SEMAPHORES(dev_priv))
 		return;
 
-	GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
+	GEM_BUG_ON(IS_GEN(dev_priv, GEN_FOREVER, 5));
 	engine->semaphore.sync_to = gen6_ring_sync_to;
 	engine->semaphore.signal = gen6_signal;
 
@@ -1949,15 +1949,15 @@  static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
 {
 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		engine->irq_enable = gen6_irq_enable;
 		engine->irq_disable = gen6_irq_disable;
 		engine->irq_seqno_barrier = gen6_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_GEN(dev_priv, 5, GEN_FOREVER)) {
 		engine->irq_enable = gen5_irq_enable;
 		engine->irq_disable = gen5_irq_disable;
 		engine->irq_seqno_barrier = gen5_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 3) {
+	} else if (IS_GEN(dev_priv, 3, GEN_FOREVER)) {
 		engine->irq_enable = i9xx_irq_enable;
 		engine->irq_disable = i9xx_irq_disable;
 	} else {
@@ -1985,7 +1985,7 @@  static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 				      struct intel_engine_cs *engine)
 {
 	/* gen8+ are only supported with execlists */
-	GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
+	GEM_BUG_ON(IS_GEN(dev_priv, 8, GEN_FOREVER));
 
 	intel_ring_init_irq(dev_priv, engine);
 	intel_ring_init_semaphores(dev_priv, engine);
@@ -2013,9 +2013,9 @@  static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 
 	engine->set_default_submission = i9xx_set_default_submission;
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		engine->emit_bb_start = gen6_emit_bb_start;
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		engine->emit_bb_start = i965_emit_bb_start;
 	else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
 		engine->emit_bb_start = i830_emit_bb_start;
@@ -2033,7 +2033,7 @@  int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	if (HAS_L3_DPF(dev_priv))
 		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		engine->init_context = intel_rcs_ctx_init;
 		engine->emit_flush = gen7_render_ring_flush;
 		if (IS_GEN6(dev_priv))
@@ -2041,7 +2041,7 @@  int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	} else if (IS_GEN5(dev_priv)) {
 		engine->emit_flush = gen4_render_ring_flush;
 	} else {
-		if (INTEL_GEN(dev_priv) < 4)
+		if (IS_GEN(dev_priv, GEN_FOREVER, 3))
 			engine->emit_flush = gen2_render_ring_flush;
 		else
 			engine->emit_flush = gen4_render_ring_flush;
@@ -2057,7 +2057,7 @@  int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		ret = intel_engine_create_scratch(engine, PAGE_SIZE);
 		if (ret)
 			return ret;
@@ -2076,7 +2076,7 @@  int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
 
 	intel_ring_default_vfuncs(dev_priv, engine);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		/* gen6 bsd needs a special wa for tail updates */
 		if (IS_GEN6(dev_priv))
 			engine->set_default_submission = gen6_bsd_set_default_submission;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 0bf97ed5ffac..a82fecd69042 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1335,13 +1335,13 @@  static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 		return;
 
 	/* Set the SDVO control regs. */
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		/* The real mode polarity is set by the SDVO commands, using
 		 * struct intel_sdvo_dtd. */
 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
 		if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 			sdvox |= HDMI_COLOR_RANGE_16_235;
-		if (INTEL_GEN(dev_priv) < 5)
+		if (IS_GEN(dev_priv, GEN_FOREVER, 4))
 			sdvox |= SDVO_BORDER_ENABLE;
 	} else {
 		sdvox = I915_READ(intel_sdvo->sdvo_reg);
@@ -1358,11 +1358,11 @@  static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
 
 	if (crtc_state->has_audio) {
-		WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
+		WARN_ON_ONCE(IS_GEN(dev_priv, GEN_FOREVER, 3));
 		sdvox |= SDVO_AUDIO_ENABLE;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER)) {
 		/* done in crtc_mode_set as the dpll_md reg must be written early */
 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
@@ -1373,7 +1373,7 @@  static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 	}
 
 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
-	    INTEL_GEN(dev_priv) < 5)
+	    IS_GEN(dev_priv, GEN_FOREVER, 4))
 		sdvox |= SDVO_STALL_SELECT;
 	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
 }
@@ -2433,7 +2433,7 @@  intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
 	struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
 
 	intel_attach_force_audio_property(&connector->base.base);
-	if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER) && IS_MOBILE(dev_priv)) {
 		intel_attach_broadcast_rgb_property(&connector->base.base);
 	}
 	intel_attach_aspect_ratio_property(&connector->base.base);
@@ -2502,7 +2502,7 @@  intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
 	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
 
 	/* gen3 doesn't do the hdmi bits in the SDVO register */
-	if (INTEL_GEN(dev_priv) >= 4 &&
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER) &&
 	    intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
 		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
 		intel_sdvo->is_hdmi = true;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 3be22c0fcfb5..fd836cee6e52 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -263,7 +263,7 @@  skl_update_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv))
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 			      plane_state->color_ctl);
 	if (key->flags) {
@@ -865,7 +865,7 @@  intel_check_sprite_plane(struct intel_plane *plane,
 	struct drm_rect *src = &state->base.src;
 	struct drm_rect *dst = &state->base.dst;
 	struct drm_rect clip = {};
-	int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
+	int max_stride = IS_GEN(dev_priv, 9, GEN_FOREVER) ? 32768 : 16384;
 	int hscale, vscale;
 	int max_scale, min_scale;
 	bool can_scale;
@@ -892,7 +892,7 @@  intel_check_sprite_plane(struct intel_plane *plane,
 	}
 
 	/* setup can_scale, min_scale, max_scale */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		/* use scaler when colorkey is not required */
 		if (!state->ckey.flags) {
 			can_scale = 1;
@@ -1012,8 +1012,8 @@  intel_check_sprite_plane(struct intel_plane *plane,
 
 		width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 
-		if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
-		    width_bytes > 4096 || fb->pitches[0] > 4096)) {
+		if (IS_GEN(dev_priv, GEN_FOREVER, 8) && (src_w > 2048 || src_h > 2048 ||
+							 width_bytes > 4096 || fb->pitches[0] > 4096)) {
 			DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 			return -EINVAL;
 		}
@@ -1031,7 +1031,7 @@  intel_check_sprite_plane(struct intel_plane *plane,
 	dst->y1 = crtc_y;
 	dst->y2 = crtc_y + crtc_h;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		ret = skl_check_plane_surface(crtc_state, state);
 		if (ret)
 			return ret;
@@ -1043,7 +1043,7 @@  intel_check_sprite_plane(struct intel_plane *plane,
 			return ret;
 
 		state->ctl = vlv_sprite_ctl(crtc_state, state);
-	} else if (INTEL_GEN(dev_priv) >= 7) {
+	} else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		ret = i9xx_check_plane_surface(state);
 		if (ret)
 			return ret;
@@ -1057,7 +1057,7 @@  intel_check_sprite_plane(struct intel_plane *plane,
 		state->ctl = g4x_sprite_ctl(crtc_state, state);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv))
 		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
 
 	return 0;
@@ -1290,11 +1290,11 @@  static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
 	    modifier != DRM_FORMAT_MOD_LINEAR)
 		return false;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		return skl_mod_supported(format, modifier);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_mod_supported(format, modifier);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		return snb_mod_supported(format, modifier);
 	else
 		return g4x_mod_supported(format, modifier);
@@ -1317,7 +1317,7 @@  bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 	if (plane_id == PLANE_CURSOR)
 		return false;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN(dev_priv, 10, GEN_FOREVER))
 		return true;
 
 	if (IS_GEMINILAKE(dev_priv))
@@ -1354,7 +1354,7 @@  intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 	}
 	intel_plane->base.state = &state->base;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		intel_plane->can_scale = true;
 		state->scaler_id = -1;
 
@@ -1380,7 +1380,7 @@  intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		plane_formats = vlv_plane_formats;
 		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
 		modifiers = i9xx_plane_format_modifiers;
-	} else if (INTEL_GEN(dev_priv) >= 7) {
+	} else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
 		if (IS_IVYBRIDGE(dev_priv)) {
 			intel_plane->can_scale = true;
 			intel_plane->max_downscale = 2;
@@ -1414,7 +1414,7 @@  intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
@@ -1435,7 +1435,7 @@  intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 	possible_crtcs = (1 << pipe);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER))
 		ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
 					       possible_crtcs, &intel_sprite_plane_funcs,
 					       plane_formats, num_plane_formats,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index b3dabc219e6a..f2223d862cb8 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1067,7 +1067,7 @@  static void intel_tv_pre_enable(struct intel_encoder *encoder,
 
 	set_color_conversion(dev_priv, color_conversion);
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN(dev_priv, 4, GEN_FOREVER))
 		I915_WRITE(TV_CLR_KNOBS, 0x00404000);
 	else
 		I915_WRITE(TV_CLR_KNOBS, 0x00606000);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62712ca..1840d9de2eac 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -435,7 +435,7 @@  u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 	/* The needed capability bits for size calculation
 	 * are not there with pre gen9 so return 128MB always.
 	 */
-	if (INTEL_GEN(dev_priv) < 9)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 8))
 		return 128 * 1024 * 1024;
 
 	return gen9_edram_size(dev_priv);
@@ -445,7 +445,7 @@  static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 {
 	if (IS_HASWELL(dev_priv) ||
 	    IS_BROADWELL(dev_priv) ||
-	    INTEL_GEN(dev_priv) >= 9) {
+	    IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 							HSW_EDRAM_CAP);
 
@@ -837,7 +837,7 @@  find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
 	{ .start = (s), .end = (e), .domains = (d) }
 
 #define HAS_FWTABLE(dev_priv) \
-	(INTEL_GEN(dev_priv) >= 9 || \
+	(IS_GEN(dev_priv, 9, GEN_FOREVER) || \
 	 IS_CHERRYVIEW(dev_priv) || \
 	 IS_VALLEYVIEW(dev_priv))
 
@@ -1253,7 +1253,7 @@  static void fw_domain_init(struct drm_i915_private *dev_priv,
 
 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
+	if (IS_GEN(dev_priv, GEN_FOREVER, 5) || intel_vgpu_active(dev_priv))
 		return;
 
 	if (IS_GEN6(dev_priv)) {
@@ -1267,7 +1267,7 @@  static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
 		dev_priv->uncore.funcs.force_wake_get =
 			fw_domains_get_with_fallback;
 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
@@ -1543,7 +1543,7 @@  static void i915_stop_engines(struct drm_i915_private *dev_priv,
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 
-	if (INTEL_GEN(dev_priv) < 3)
+	if (IS_GEN(dev_priv, GEN_FOREVER, 2))
 		return;
 
 	for_each_engine_masked(engine, dev_priv, engine_mask, id)
@@ -1883,9 +1883,9 @@  static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 	if (!i915_modparams.reset)
 		return NULL;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN(dev_priv, 8, GEN_FOREVER))
 		return gen8_reset_engines;
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN(dev_priv, 6, GEN_FOREVER))
 		return gen6_reset_engines;
 	else if (IS_GEN5(dev_priv))
 		return ironlake_do_reset;
@@ -1893,7 +1893,7 @@  static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 		return g4x_do_reset;
 	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
 		return g33_do_reset;
-	else if (INTEL_GEN(dev_priv) >= 3)
+	else if (IS_GEN(dev_priv, 3, GEN_FOREVER))
 		return i915_do_reset;
 	else
 		return NULL;
@@ -1996,7 +1996,7 @@  intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
 
 	if (HAS_FWTABLE(dev_priv)) {
 		fw_domains = __fwtable_reg_read_fw_domains(offset);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
 		fw_domains = __gen6_reg_read_fw_domains(offset);
 	} else {
 		WARN_ON(!IS_GEN(dev_priv, 2, 5));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index 7a0d1e17c1ad..70de1cddce32 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -204,12 +204,12 @@  static int gpu_set(struct drm_i915_gem_object *obj,
 		return PTR_ERR(cs);
 	}
 
-	if (INTEL_GEN(i915) >= 8) {
+	if (IS_GEN(i915, 8, GEN_FOREVER)) {
 		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 		*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
 		*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
 		*cs++ = v;
-	} else if (INTEL_GEN(i915) >= 4) {
+	} else if (IS_GEN(i915, 4, GEN_FOREVER)) {
 		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 		*cs++ = 0;
 		*cs++ = i915_ggtt_offset(vma) + offset;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 56a803d11916..4ef721e840da 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -159,7 +159,7 @@  static int gpu_fill(struct drm_i915_gem_object *obj,
 	}
 
 	flags = 0;
-	if (INTEL_GEN(vm->i915) <= 5)
+	if (IS_GEN(vm->i915, GEN_FOREVER, 5))
 		flags |= I915_DISPATCH_SECURE;
 
 	err = engine->emit_bb_start(rq,
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index f32aa6bb79e2..cbbacf718c8b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -355,7 +355,7 @@  static int igt_partial_tiling(void *arg)
 		    tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
 			continue;
 
-		if (INTEL_GEN(i915) <= 2) {
+		if (IS_GEN(i915, GEN_FOREVER, 2)) {
 			tile.height = 16;
 			tile.width = 128;
 			tile.size = 11;
@@ -370,9 +370,9 @@  static int igt_partial_tiling(void *arg)
 			tile.size = 12;
 		}
 
-		if (INTEL_GEN(i915) < 4)
+		if (IS_GEN(i915, GEN_FOREVER, 3))
 			max_pitch = 8192 / tile.width;
-		else if (INTEL_GEN(i915) < 7)
+		else if (IS_GEN(i915, GEN_FOREVER, 6))
 			max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width;
 		else
 			max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width;
@@ -385,7 +385,7 @@  static int igt_partial_tiling(void *arg)
 			if (err)
 				goto out_unlock;
 
-			if (pitch > 2 && INTEL_GEN(i915) >= 4) {
+			if (pitch > 2 && IS_GEN(i915, 4, GEN_FOREVER)) {
 				tile.stride = tile.width * (pitch - 1);
 				err = check_partial_mapping(obj, &tile, end);
 				if (err == -EINTR)
@@ -394,7 +394,7 @@  static int igt_partial_tiling(void *arg)
 					goto out_unlock;
 			}
 
-			if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
+			if (pitch < max_pitch && IS_GEN(i915, 4, GEN_FOREVER)) {
 				tile.stride = tile.width * (pitch + 1);
 				err = check_partial_mapping(obj, &tile, end);
 				if (err == -EINTR)
@@ -404,7 +404,7 @@  static int igt_partial_tiling(void *arg)
 			}
 		}
 
-		if (INTEL_GEN(i915) >= 4) {
+		if (IS_GEN(i915, 4, GEN_FOREVER)) {
 			for_each_prime_number(pitch, max_pitch) {
 				tile.stride = tile.width * pitch;
 				err = check_partial_mapping(obj, &tile, end);
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index d1d2c2456f69..b0a28ac48854 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -136,7 +136,7 @@  static int emit_recurse_batch(struct hang *h,
 	}
 
 	batch = h->batch;
-	if (INTEL_GEN(i915) >= 8) {
+	if (IS_GEN(i915, 8, GEN_FOREVER)) {
 		*batch++ = MI_STORE_DWORD_IMM_GEN4;
 		*batch++ = lower_32_bits(hws_address(hws, rq));
 		*batch++ = upper_32_bits(hws_address(hws, rq));
@@ -150,7 +150,7 @@  static int emit_recurse_batch(struct hang *h,
 		*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
 		*batch++ = lower_32_bits(vma->node.start);
 		*batch++ = upper_32_bits(vma->node.start);
-	} else if (INTEL_GEN(i915) >= 6) {
+	} else if (IS_GEN(i915, 6, GEN_FOREVER)) {
 		*batch++ = MI_STORE_DWORD_IMM_GEN4;
 		*batch++ = 0;
 		*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -163,7 +163,7 @@  static int emit_recurse_batch(struct hang *h,
 		*batch++ = MI_ARB_CHECK;
 		*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
 		*batch++ = lower_32_bits(vma->node.start);
-	} else if (INTEL_GEN(i915) >= 4) {
+	} else if (IS_GEN(i915, 4, GEN_FOREVER)) {
 		*batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 		*batch++ = 0;
 		*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -193,7 +193,7 @@  static int emit_recurse_batch(struct hang *h,
 	i915_gem_chipset_flush(h->i915);
 
 	flags = 0;
-	if (INTEL_GEN(vm->i915) <= 5)
+	if (IS_GEN(vm->i915, GEN_FOREVER, 5))
 		flags |= I915_DISPATCH_SECURE;
 
 	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 2f6367643171..bfa4d5d4493d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -173,7 +173,7 @@  int intel_uncore_live_selftests(struct drm_i915_private *i915)
 	/* Confirm the table we load is still valid */
 	err = intel_fw_table_check(i915->uncore.fw_domains_table,
 				   i915->uncore.fw_domains_table_entries,
-				   INTEL_GEN(i915) >= 9);
+				   IS_GEN(i915, 9, GEN_FOREVER));
 	if (err)
 		return err;